High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian‐Mao

doi:10.1021/acsnano.7b00861

Cited by 143 publications

(163 citation statements)

References 39 publications

Supporting

Mentioning

159

Contrasting

Order By: Relevance

“…Using randomly oriented or aligned CNT array films, various types of CNT thin-film FETs have been fabricated [9][10][11][12][13] . However, hindered by the limited performance of nanotube FETs, the operation speed of CNT integrated circuits (ICs) [20][21][22][23][24][25][26][27][28][29][30][31] typically falls short of their expected terahertz potential, and that achieved by Si CMOS circuits (gigahertz), by several orders of magnitude. Notably, CNT-based ring oscillators (ROs) with an oscillation frequency (f o ) of 282 MHz have recently been reported 32 .…”

mentioning

confidence: 99%

Gigahertz integrated circuits based on carbon nanotube films

et al. 2017

Self Cite

View full text Add to dashboard Cite

Carbon nanotube (CNT)-based electronics are a potential candidate to replace silicon complementary metal-oxide-semiconductor (CMOS) technology, which will soon meet its performance limit at the 7 or 5 nm technology node 1,2 . Prototype device studies using individual CNTs have shown that nanotube electronics have the potential to outperform Si CMOS technology in both performance and power consumption [3][4][5][6] , and are even close to the theoretical limits for all field-effect-transistor(FET)-based binary switches 7,8 . Recently, FETs were fabricated using aligned CNT arrays, and shown to have a higher channel conductance (at a lower bias) than that of Si CMOS FETs 9 . However, the key performance metrics reported for such CNT FETs, including on-state current density (I on ) and transconductance (g m ), are still substantially lower than those of conventional Si CMOS FETs at the same characteristic length [9][10][11][12][13] . The ideal material system for high-performance CNT electronics has been identified as a parallel array film of intrinsic pure semiconductor single-walled nanotubes of a single chirality with a diameter of approximately 1.3 nm and no defects, and a tube-tube spacing of 5-8 nm (ref. 14 ). Although such an ideal material system is yet to be realized, many breakthroughs in the purification and controlled synthesis of CNTs have been made in recent years [15][16][17][18][19] , suggesting the possibility of achieving the required nanotube purity and array density before 2020 14 . Using randomly oriented or aligned CNT array films, various types of CNT thin-film FETs have been fabricated [9][10][11][12][13] . However, hindered by the limited performance of nanotube FETs, the operation speed of CNT integrated circuits (ICs) 20-31 typically falls short of their expected terahertz potential, and that achieved by Si CMOS circuits (gigahertz), by several orders of magnitude. Notably, CNT-based ring oscillators (ROs) with an oscillation frequency (f o ) of 282 MHz have recently been reported 32 . However, CNT-thin-film-based ICs typically have a working frequency of less than 1 MHz, which might be useful for flexible electronics, but is not suitable for mainstream high-performance CMOS technology 33 . In this study, we used a randomly oriented CNT film to build CNT FETs and ICs, fabricating, in particular, five-stage ROs with f o of up to 5.54 GHz. The random CNT film is essentially the same as a network film, but here we used the term 'random film' to emphasize that our FETs are contact dominated and have a different transport mechanism to that of junction-dominated network-type FETs 34,35 . In principle, aligned CNT arrays would provide better device performance, but it remains a challenge to obtain wafer-scale aligned CNT arrays with high uniformity, high density and high semiconductor purity for constructing high-performance ICs. Although it is not the ideal scheme, the FET-and IC-based random CNT film can nevertheless provide a feasible demonstration to assess the floor-level performance (f...

show abstract

mentioning

confidence: 99%

Gigahertz integrated circuits based on carbon nanotube films

et al. 2017

Self Cite

View full text Add to dashboard Cite

show abstract

“…[5][6][7][8][9][10][11][12] In particular, highperformance complementary metal-oxidesemiconductor (CMOS) FETs have been realized on CNT films through dopingfree technology. [10] Researchers have also demonstrated various kinds of ICs based on solution-derived CNT films, including fundamental logic and arithmetic gates, ring oscillators and even medium-scale ICs, [9][10][11] which shows the development potential of CNT film ICs in digital applications. However, the vast majority of ICs realized on CNT films are arithmetic/ logic units, and few works have addressed static random access memory (SRAM), which is an indispensable part of actual digital ICs.…”

mentioning

confidence: 99%

High‐Performance and Radiation‐Hard Carbon Nanotube Complementary Static Random‐Access Memory

Zhu

Zhang

Peng

2019

Adv Elect Materials

Self Cite

View full text Add to dashboard Cite

development of solution-derived CNT films with high semiconducting purity and high quality. [5][6][7][8][9][10][11][12] In particular, highperformance complementary metal-oxidesemiconductor (CMOS) FETs have been realized on CNT films through dopingfree technology. [10] Researchers have also demonstrated various kinds of ICs based on solution-derived CNT films, including fundamental logic and arithmetic gates, ring oscillators and even medium-scale ICs, [9][10][11] which shows the development potential of CNT film ICs in digital applications. However, the vast majority of ICs realized on CNT films are arithmetic/ logic units, and few works have addressed static random access memory (SRAM), which is an indispensable part of actual digital ICs. As the fastest and most expensive memory, SRAM arrays typically act as caches in the central processing unit (CPU) and should be a necessary component for constructing high-performance CNT-based CPUs or microcontroller units (MCUs) and other complete digital systems. Hersam and coworkers demonstrated a six-transistor (6-T) CMOS SRAM cell based on a CNT film for the first time. [12] However, the reported SRAMs were built based on bottom-gated CNT FETs, and measurements of the dynamic characteristics were absent. Furthermore, at the present stage, none of the CNT-based ICs, including SRAM, showed any actual advantage over conventional ICs, regardless of speed, power dissipation, or integrated density. Therefore, it is still an important issue to explore and demonstrate the potential advantages of CNT-based ICs.A single-walled CNT (SWCNT) possesses cross-linked, strong CC bonds at the nanometer scale and low atomic numbers and is an especially attractive material for building radiationhard FETs. [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28] Furthermore, additional advantages in the device structure of CNT film FETs reinforce the radiation hardness. For example, a multichannel structure is beneficial for the resistance of single event effects (SEEs), and radiation-induced charge accumulation in isolation regions is completely avoided in CNT ICs because they do not require an isolation region. [24][25][26][27] Many previous reports have studied the total ionizing dose (TID) property of CNT-based FETs by using various radiation sources including ions, gamma radiation, protons, and electrons. [23,24] Very recently, the radiation-resistant properties of complementary CNT FETs and inverters have been explored by two different groups. [26,27] However, there are still obvious deficiencies in the Significant progress on carbon-nanotube (CNT) electronics means that they are a serious candidate for use in high-performance integrated circuits (ICs). However, few works have focused on fabricating and exploring CNT complementary metal-oxide-semiconductor (CMOS) static random-access memory (SRAM), which is an integral part of most digital ICs. High-performance complementary top-gated field-effect transistors (FETs) are fabricated through a doping-free technology based on so...

show abstract

“…[66] High-k dielectric materials, such as HfO 2 and Al 2 O 3 , are regarded as the ideal dielectrics for constructing high-performance SWCNT transistors. Previous studies have shown that printed SWCNT TFTs have high mobility up to 20 cm 2 V −1 s −1 , and it is beneficial to associate sc-SWCNTs with highly efficient gate dielectrics to maximize their performance as channel materials.…”

Section: Resultsmentioning

confidence: 99%

High‐Performance Partially Printed Hybrid CMOS Inverters Based on Indium‐Zinc‐Oxide and Chirality Enriched Carbon Nanotube Thin‐Film Transistors

Luo

Xie²,

Wei

et al. 2019

Adv Elect Materials

View full text Add to dashboard Cite

Inkjet printing is a promising technique to fabricate thin-film transistors (TFTs) and integrated complementary metal-oxidesemiconductor (CMOS) circuits because of its patterned Complementary metal-oxide-semiconductor (CMOS) inverters with low power consumption and high noise immunity are essential for realizing practical applications of printed logic gates and circuits. However, the performance of existing printed CMOS inverters is still unsatisfactory because p-type and n-type transistors do not match well. This work demonstrates novel low-voltage and high-performance CMOS inverters using partially printed thin-film transistors (TFTs) on 50 nm HfO 2 /Si substrates based on n-type indium zinc oxides (IZOs) and p-type chirality enriched (9,8) semiconducting single-walled carbon nanotubes (SWCNTs). The high-k dielectric materials grown using atomic layer deposition and (9,8) SWCNTs with relatively large band gaps help to match the characteristics of p-type and n-type transistors-the IZO and SWCNT TFTs exhibit similar mobility on/off ratio, small hysteresis, and low sub-threshold swing at low operating voltages. The hybrid CMOS inverters demonstrate excellent performance with the highest voltage gain up to 45, the largest noise margin of 83% at 1/2 V dd , and the lowest static power consumption of 0.4 µW at V dd of 2 V among recently reported printed CMOS inverters under relatively low annealing temperatures (300 °C). The strategies demonstrated here can be considered as general approaches to realize a new generation of high-performance printed logic gates and circuits. Printable ElectronicsThe ORCID identification number(s) for the author(s) of this article can be found under https://doi.

show abstract

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films

Cited by 143 publications

References 39 publications

Gigahertz integrated circuits based on carbon nanotube films

Gigahertz integrated circuits based on carbon nanotube films

High‐Performance and Radiation‐Hard Carbon Nanotube Complementary Static Random‐Access Memory

High‐Performance Partially Printed Hybrid CMOS Inverters Based on Indium‐Zinc‐Oxide and Chirality Enriched Carbon Nanotube Thin‐Film Transistors

Contact Info

Product

Resources

About