Single-walled carbon nanotubes (CNTs) may enable the fabrication of integrated circuits smaller than 10 nanometers, but this would require scalable production of dense and electronically pure semiconducting nanotube arrays on wafers. We developed a multiple dispersion and sorting process that resulted in extremely high semiconducting purity and a dimension-limited self-alignment (DLSA) procedure for preparing well-aligned CNT arrays (within alignment of 9 degrees) with a tunable density of 100 to 200 CNTs per micrometer on a 10-centimeter silicon wafer. Top-gate field-effect transistors (FETs) fabricated on the CNT array show better performance than that of commercial silicon metal oxide–semiconductor FETs with similar gate length, in particular an on-state current of 1.3 milliamperes per micrometer and a recorded transconductance of 0.9 millisiemens per micrometer for a power supply of 1 volt, while maintaining a low room-temperature subthreshold swing of <90 millivolts per decade using an ionic-liquid gate. Batch-fabricated top-gate five-stage ring oscillators exhibited a highest maximum oscillating frequency of >8 gigahertz.

Near ballistic n-type single-walled carbon nanotube field-effect transistors (SWCNT FETs) have been fabricated with a novel self-aligned gate structure and a channel length of about 120 nm on a SWCNT with a diameter of 1.5 nm. The device shows excellent on- and off-state performance, including high transconductance of up to 25 microS, small subthreshold swing of 100 mV/dec, and gate delay time of 0.86 ps, suggesting that the device can potentially work at THz regime. Quantitative analysis on the electrical characteristics of a long channel device fabricated on the same SWCNT reveals that the SWCNT has a mean-free-path of 191 nm, and the electron mobility of the device reaches 4650 cm(2)/Vs. When benchmarked by the metric CV/ I vs Ion/Ioff, the n-type SWCNT FETs show significantly better off-state leakage than that of the Si-based n-type FETs with similar channel length. An important advantage of this self-aligned gate structure is that any suitable gate materials can be used, and in particular it is shown that the threshold voltage of the self-aligned n-type FETs can be adjusted by selecting gate metals with different work functions.

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Carbon nanotube (CNT)-based electronics are a potential candidate to replace silicon complementary metal-oxide-semiconductor (CMOS) technology, which will soon meet its performance limit at the 7 or 5 nm technology node 1,2 . Prototype device studies using individual CNTs have shown that nanotube electronics have the potential to outperform Si CMOS technology in both performance and power consumption [3][4][5][6] , and are even close to the theoretical limits for all field-effect-transistor(FET)-based binary switches 7,8 . Recently, FETs were fabricated using aligned CNT arrays, and shown to have a higher channel conductance (at a lower bias) than that of Si CMOS FETs 9 . However, the key performance metrics reported for such CNT FETs, including on-state current density (I on ) and transconductance (g m ), are still substantially lower than those of conventional Si CMOS FETs at the same characteristic length [9][10][11][12][13] . The ideal material system for high-performance CNT electronics has been identified as a parallel array film of intrinsic pure semiconductor single-walled nanotubes of a single chirality with a diameter of approximately 1.3 nm and no defects, and a tube-tube spacing of 5-8 nm (ref. 14 ). Although such an ideal material system is yet to be realized, many breakthroughs in the purification and controlled synthesis of CNTs have been made in recent years [15][16][17][18][19] , suggesting the possibility of achieving the required nanotube purity and array density before 2020 14 . Using randomly oriented or aligned CNT array films, various types of CNT thin-film FETs have been fabricated [9][10][11][12][13] . However, hindered by the limited performance of nanotube FETs, the operation speed of CNT integrated circuits (ICs) 20-31 typically falls short of their expected terahertz potential, and that achieved by Si CMOS circuits (gigahertz), by several orders of magnitude. Notably, CNT-based ring oscillators (ROs) with an oscillation frequency (f o ) of 282 MHz have recently been reported 32 . However, CNT-thin-film-based ICs typically have a working frequency of less than 1 MHz, which might be useful for flexible electronics, but is not suitable for mainstream high-performance CMOS technology 33 . In this study, we used a randomly oriented CNT film to build CNT FETs and ICs, fabricating, in particular, five-stage ROs with f o of up to 5.54 GHz. The random CNT film is essentially the same as a network film, but here we used the term 'random film' to emphasize that our FETs are contact dominated and have a different transport mechanism to that of junction-dominated network-type FETs 34,35 . In principle, aligned CNT arrays would provide better device performance, but it remains a challenge to obtain wafer-scale aligned CNT arrays with high uniformity, high density and high semiconductor purity for constructing high-performance ICs. Although it is not the ideal scheme, the FET-and IC-based random CNT film can nevertheless provide a feasible demonstration to assess the floor-level performance (f...

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