High-performance deep-submicrometer Si MOSFETs using vertical doping engineering

Yan, Ran; Lee, K.F.; Jeon, Dae‐Young; Kim, Y.O.; Tennant, D. M.; Westerwick, E.H.; Chin, G. Y.; Morris, M.D.; Early, K.; Mulgrew, P. P.

doi:10.1109/16.163487

“…Over the ensuing 22 years, feature sizes have evolved from 6 to 0.6 µ and the trend shows no sign of abating [4][5][6][7][8][9][10] . In this paper, I shall examine what we have learned from the past 22 years of technology evolution, and shall discuss to what extent these same trends may cont inue into the future.…”

Section: Introductionmentioning

confidence: 99%

Scaling of MOS Technology to Submicrometer Feature Sizes

2002

Analog VLSI

0

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Industries based on MOS technology now play a prominent role in t he developed and the developing world. j\fore importantly, MOS techn ology drives a large proportion of innovation in many technologies . It is likely th at the course of technological development depends more on the capability of MOS technology than on any other technical factor . T herefore, it is worthwhile investigating the na.ture and limits of future improvements to MOS fabrication. The key to improved MOS technology is r eduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at t he system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude wi th som e remarks on the system-level implications of fea.ture size as the minimum size approach es physical limits.

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Scaling of MOS technology to submicrometer feature sizes

Mead

¹

1994

Analog Integr Circ Sig Process

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Industries based on MOS technology now play a prominent role in t he developed and the developing world. j\fore importantly, MOS techn ology drives a large proportion of innovation in many technologies . It is likely th at the course of technological development depends more on the capability of MOS technology than on any other technical factor . T herefore, it is worthwhile investigating the na.ture and limits of future improvements to MOS fabrication. The key to improved MOS technology is r eduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at t he system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude wi th som e remarks on the system-level implications of fea.ture size as the minimum size approach es physical limits. IntroductionIt is always difficult . to nredict the future; few attemp ts to do so have met with resounding su ccess. One remarkable example of successful prediction is the exponential increase in complexity of integrated circuits, first noted by Gordon E . !vioor e. As we contemplate the ongoing evolution of this great technology, many questions arise: Can the trend continue? Will single-chip systems attain levels of complexity that render present system archit ectures unworkable [lj? vVill digital t.echniques completely replace analog methods [2]"7 The answers to these questions depend critically on the properties of the individual transistor s that provide the essential active functions, without which no interesting system beh avior is possible. Integrated-circuit density is increased by a reduction in the size of elementary feat.ures of the underlying structures; therefore, any discussion of the capabilities of future technologies must rely on an understanding of how the properties of transistors evolve as the transistor s' dimensions are made smaller.Elsewhere [3], we described the factors that limit how small an MOS transistor *Reproduced from Journal of VLSI Signal P rocessing, 8 , 9-25 (1994) Kluwer Academic Publishers, Boston. ~fanufacture d in The Netherlands.

show abstract

Scaling of MOS technology to submicrometer feature sizes

Mead

¹

1994

Journal of VLSI Signal Processing

View full text Add to dashboard Cite

Industries based on MOS technology now play a prominent role in t he developed and the developing world. j\fore importantly, MOS techn ology drives a large proportion of innovation in many technologies . It is likely th at the course of technological development depends more on the capability of MOS technology than on any other technical factor . T herefore, it is worthwhile investigating the na.ture and limits of future improvements to MOS fabrication. The key to improved MOS technology is r eduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at t he system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude wi th som e remarks on the system-level implications of fea.ture size as the minimum size approach es physical limits. IntroductionIt is always difficult . to nredict the future; few attemp ts to do so have met with resounding su ccess. One remarkable example of successful prediction is the exponential increase in complexity of integrated circuits, first noted by Gordon E . !vioor e. As we contemplate the ongoing evolution of this great technology, many questions arise: Can the trend continue? Will single-chip systems attain levels of complexity that render present system archit ectures unworkable [lj? vVill digital t.echniques completely replace analog methods [2]"7 The answers to these questions depend critically on the properties of the individual transistor s that provide the essential active functions, without which no interesting system beh avior is possible. Integrated-circuit density is increased by a reduction in the size of elementary feat.ures of the underlying structures; therefore, any discussion of the capabilities of future technologies must rely on an understanding of how the properties of transistors evolve as the transistor s' dimensions are made smaller.Elsewhere [3], we described the factors that limit how small an MOS transistor *Reproduced from Journal of VLSI Signal P rocessing, 8 , 9-25 (1994) Kluwer Academic Publishers, Boston. ~fanufacture d in The Netherlands.

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High-performance deep-submicrometer Si MOSFETs using vertical doping engineering

Cited by 5 publications

References 3 publications

Scaling of MOS Technology to Submicrometer Feature Sizes

Scaling of MOS Technology to Submicrometer Feature Sizes

Scaling of MOS technology to submicrometer feature sizes

Scaling of MOS technology to submicrometer feature sizes

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