Scaling of MOS technology to submicrometer feature sizes

Mead, C. A.

doi:10.1007/bf01250732

Cited by 53 publications

(23 citation statements)

References 36 publications

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“…The initial silicon was then doped with boron with a concentration of 1 x 10 14 atom/cm 3 . The formation of BOX was done by depositing 40 nm oxide thickness (tBOX).…”

Section: Process and Device Structurementioning

confidence: 99%

“…High leakage current (IOFF) in nano-scale regimes is becoming a significant contributor to the power dissipation of the MOSFET device [2]. This increase in IOFF is typically due to the charge-sharing effect caused by drain-induced barrier lowering (DIBL) or due to deep channel punchthrough currents [3]. As the channel width decreases, both the threshold voltage (VTH) and leakage current (IOFF) will be modulated by the width of the transistor, giving rise to a significant narrow-width effect.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of process parameter variations on leakage current in SOI vertical double gate MOSFET device

Kaharudin¹,

Salehuddin²,

Zain³

et al. 2016

J. Mech, Eng, Sci.

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This paper presents a study of optimizing input process parameters on leakage current (IOFF) in a silicon-on-insulator (SOI) Vertical Double-Gate (DG) Metal Oxide FieldEffect-Transistor (MOSFET) by using the L36 Taguchi method. The performance of the SOI Vertical DG-MOSFET device is evaluated in terms of its lowest leakage current (IOFF) value. An orthogonal array (OA), main effects, signal-to-noise ratio (SNR) and analysis of variance (ANOVA) are utilized in order to analyse the effect of input process parameter variation on the leakage current (IOFF). Based on the results, the minimum leakage current ((IOFF) of the SOI Vertical DG-MOSFET is observed to be 0.009 nA/µm or 9 ρA/µm while keeping the drive current (ION) value at 434 µA/µm. Both the drive current (ION) and leakage current (IOFF) values yield a higher ION/IOFF ratio (48.22 x 10 6 ) for low power consumption application. Meanwhile, the polysilicon doping tilt angle and polysilicon doping energy are recognized as the most dominant factors, contributing factor effects percentages of 59% and 25% respectively.

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“…The initial silicon was then doped with boron with a concentration of 1 x 10 14 atom/cm 3 . The formation of BOX was done by depositing 40 nm oxide thickness (tBOX).…”

Section: Process and Device Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimization of process parameter variations on leakage current in SOI vertical double gate MOSFET device

Kaharudin¹,

Salehuddin²,

Zain³

et al. 2016

J. Mech, Eng, Sci.

View full text Add to dashboard Cite

show abstract

“…Additionally, a dense network of such transistors could be slowed down by the flow of current through extremely narrow wires from one device to the next. Detailed treatments of the fundamental limitations upon small electronic circuitry [4]- [9], [49] and of the scaling problem for FET's may be found elsewhere in the literature [39], [109], including this issue of the Proceedings [43], [171].…”

Section: B Obstacles To Further Miniaturization Of Fet'smentioning

confidence: 99%

Overview of nanoelectronic devices

et al. 1997

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“…We fit these data with an FN fit [16,22]: where lg is the gate current; V ox is the oxide voltage; Vt = 928V is consistent with a recent survey [18] of Si0 2 tunneling, given the 350A gate oxide; and <p is a fit parameter. We also show an empirical fit , in which we add a built-in potential, Vbi, to the FN equation, to fit the experimental data more closely: ( 14.3) where {-Vii , and V 0 are fit constants.…”

Section: The Tunneling Equationmentioning

confidence: 99%

“…We typically operate the synapses in their subthreshold regime (18], and select either drain current or source current as the synapse output. We choose subthreshold operation for three reasons.…”

Section: The Synapsesmentioning

confidence: 99%

Floating-Gate MOS Synapse Transistors

Diorio

Hasler

Minch

et al.

The Springer International Series in Engineering and Computer Science

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Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices, such as EEP ROM transistors. typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although floatinggate transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through Si02 , these devices have not seen wide use as memory elements in silicon learning systems.We have fabricated synapse transistors that not only possess nonvolatile analog storage, and compute locally their own memory updates, but also permit simultaneous memory reading and writing, and compute locally the product of their stored memory value and the applied input. To ensure nonvolatile storage, we employ standard floating-gate MOS technology, but we adapt the physical processes that write the memory to perform a local learning function. Although the Si02 electron transport still is difficult, and does require high voltages, because our devices integrate both memory storage and local computation within a single device, we expect them to find wide application iil silicon learning systems.We call our devices synapse transistors because, like neural synapses [11], they compute the product of their stored analog memory and the applied input. Also like neural synapses, they can learn from the input signal, without

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Scaling of MOS technology to submicrometer feature sizes

Cited by 53 publications

References 36 publications

Optimization of process parameter variations on leakage current in SOI vertical double gate MOSFET device

Optimization of process parameter variations on leakage current in SOI vertical double gate MOSFET device

Overview of nanoelectronic devices

Floating-Gate MOS Synapse Transistors

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