2015
DOI: 10.1109/ted.2014.2385062
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High-Performance Enhancement-Mode Al<sub>2</sub>O<sub>3</sub>/AlGaN/GaN-on-Si MISFETs With 626 MW/<inline-formula> <tex-math notation="LaTeX">$\mathrm{cm}^{2}$ </tex-math></inline-formula> Figure of Merit

Abstract: In this paper, the partial gate recess for performance improvement of enhancement-mode (E-mode) GaN power devices is experimentally demonstrated. The gate recess with a careful control of the recess depth was performed with an optimized recessed barrier thickness of ∼1.5 nm that is thin enough to completely deplete the 2-D electron gas channel in the gate region. Meanwhile, the remaining barrier preserves the as-grown quantum well of the heterostructure physically intact and thus, effectively mitigates the lat… Show more

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Cited by 77 publications
(24 citation statements)
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“…For power switching applications, the enhancement-mode (E-mode) transistors are highly preferred rather than the depletion-mode (D-mode) devices for the inherent fail-safe operation and simple gate driver circuitry. Despite the various technologies proposed to realize E-mode, GaN HFETs such as p-cap gate [2, 3], fluorine plasma ion implantation [4], and cascode technology [5], the MOSFET with partially or fully recessed gate is considered as a promising candidate because of its high-threshold voltage ( V TH ), large gate swing for improved fail-safe capability [6, 7], and low on-resistance [8]. Moreover, the MOS-gate is compatible with the mainstream gate driver ICs.…”
Section: Introductionmentioning
confidence: 99%
“…For power switching applications, the enhancement-mode (E-mode) transistors are highly preferred rather than the depletion-mode (D-mode) devices for the inherent fail-safe operation and simple gate driver circuitry. Despite the various technologies proposed to realize E-mode, GaN HFETs such as p-cap gate [2, 3], fluorine plasma ion implantation [4], and cascode technology [5], the MOSFET with partially or fully recessed gate is considered as a promising candidate because of its high-threshold voltage ( V TH ), large gate swing for improved fail-safe capability [6, 7], and low on-resistance [8]. Moreover, the MOS-gate is compatible with the mainstream gate driver ICs.…”
Section: Introductionmentioning
confidence: 99%
“…The R on,sp and breakdown voltage characteristics of both devices are plotted in Fig. in comparison with other reported normally off GaN devices [].…”
Section: Resultsmentioning
confidence: 99%
“…Being attracted, the gate recess technology has suffered from A plasma‐induced physical damage to the recessed surface and high interface trap density. It has been reported by several groups that the channel surface defects not only degraded the channel mobility but also caused trapping problems leading to hysteresis and threshold are voltage ( V th ) drift during switching operation . Such trapping issues play a very important role when MIS‐gate structures are used because of the high interface and bulk traps in the insulated gate.…”
Section: Introductionmentioning
confidence: 99%
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“…26 The SiN x passivation layer of 100 nm was deposited by PECVD prior to the 20 nm ALD-Al 2 O 3 gate dielectric. The hybrid gate recess technology 13 was performed to precisely control the recess depth. The recessed-barrier-thickness T was then confirmed to be 4 nm by AFM that is well reconcile with the optimal trench depth obtained by simulation.…”
Section: Device Fabrication and Measurement Resultsmentioning
confidence: 99%