High-performance hardware monitors to protect network processors from data plane attacks

Abstract

The Internet represents an essential communication infrastructure that needs to be protected from malicious attacks. Modern network routers are typically implemented using embedded multi-core network processors that are inherently vulnerable to attack. Hardware monitor subsystems, which can verify the behavior of a router's packet processing system at runtime, can be used to identify and respond to an ever-changing range of attacks. While hardware monitors have primarily been described in the context of generalpurpose computing, our work focuses on two important aspects that are relevant to the embedded networking domain: We present the design and prototype implementation of a high-performance monitor that can track each processor instruction with low memory overhead. Additionally, our monitor is capable of defending against attacks on processors with a Harvard architecture, the dominant contemporary network processor organization. We demonstrate that our monitor architecture provides no network slowdown in the absence of an attack and provides the capability to drop attack packets without otherwise affecting regular network traffic when an attack occurs.

Dynamic Hardware Monitors for Network Processor Protection

“…Hardware monitoring has been studied extensively for embedded systems [15]- [17] and has also been proposed for use in network processors [6]. In our recent work, we describe a high-performance implementation of such a hardware monitoring system that can meet the throughput demands of a network processor with a single processing core [18].…”

“…In addition, attacks on network processors have been shown both on systems that are based on von Neumann architecture [3], leading to arbitrary code execution, and on systems based on Harvard architecture [18], leading to return-to-libc attacks.…”

“…Hardware monitors for single core network processor systems have been demonstrated in prior work [3], [18]. These solutions, however, do not address three critical problems that appear in practical network processor systems:…”

“…Our benchmark analysis shows that this is the typical case for NP applications. Full details of graph generation, including a detailed example, are shown in [18].…”