Physically Unclonable Functions (PUFs) are a special class of circuits used for challenge-response authentication. The challenge-response pair for PUFs should be mathematically unpredictable, but must be reliable and remain unvarying. The reliability of PUFs implemented in CMOS circuits is frequently compromised by environmental conditions such as voltage and temperature. In this paper, we propose two methods for improving the reliability of delay based PUFs, by reducing temperature sensitivity. The first method focuses on improving the gate overdrive (VGS − Vt(T )), by operating the PUF at an optimized supply voltage (V DD ), also called as ZTC (Zero Temperature Coefficient) voltage. The optimum supply voltage for a 24 stage PUF is almost 23% lower than the nominal supply voltage in 45nm CMOS technology. The second method exploits the negative temperature coefficient (TCR) property of n + and p + polysilicon placed as source feedback resistors. A 16% improvement in reliability has been demonstrated for both the methods. Moreover, we also demonstrate that these design optimizations do not compromise the PUF uniqueness.

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The Internet represents an essential communication infrastructure that needs to be protected from malicious attacks. Modern network routers are typically implemented using embedded multi-core network processors that are inherently vulnerable to attack. Hardware monitor subsystems, which can verify the behavior of a router's packet processing system at runtime, can be used to identify and respond to an ever-changing range of attacks. While hardware monitors have primarily been described in the context of generalpurpose computing, our work focuses on two important aspects that are relevant to the embedded networking domain: We present the design and prototype implementation of a high-performance monitor that can track each processor instruction with low memory overhead. Additionally, our monitor is capable of defending against attacks on processors with a Harvard architecture, the dominant contemporary network processor organization. We demonstrate that our monitor architecture provides no network slowdown in the absence of an attack and provides the capability to drop attack packets without otherwise affecting regular network traffic when an attack occurs.

The importance of the Internet for society is increasing. To ensure a functional Internet, its routers need to operate correctly. However, the need for router flexibility has led to the use of softwareprogrammable network processors in routers, which exposes these systems to data plane attacks. Recently, hardware monitors have been introduced into network processors to verify the expected behavior of processor cores at run time. If instruction-level execution deviates from the expected sequence, an attack is identified, triggering processor core recovery efforts. In this manuscript, we describe a scalable network processor monitoring system that supports the reallocation of hardware monitors to processor cores in response to workload changes. The scalability of our monitoring architecture is demonstrated using theoretical models, simulation, and router system-level experiments implemented on an FPGA-based hardware platform. For a system with four processor cores and six monitors, the monitors result in a 6% logic and 38% memory bit overhead versus the processor's core logic and instruction storage. No slowdown of system throughput due to monitoring is reported.Index Terms-network security, network infrastructure, data plane attack, hardware monitor, multicore processor, FPGA 0018-9340 (c)

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