On improving reliability of delay based Physically Unclonable Functions under temperature variations

Kumar, Raghavan; Chandrikakutty, Harikrishnan Kumarapillai; Kundu, Sandip

doi:10.1109/hst.2011.5955012

Cited by 27 publications

(8 citation statements)

References 21 publications

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“…Results also showed that only SVC-OPC could generate longer keys that pass the NIST tests. While reliability was lower than P-OPC, it is better than the conventional approach (21% improvement) and could still be improved with variation-resistant circuit designs [11], [12].…”

Section: Discussionmentioning

confidence: 86%

“…Some authors have also investigated better circuit designs and supply voltage biasing [9], [10] that enhance the random variations within the architecture for better PUF uniqueness and/or reliability. Circuit resistance to environmental variation has also been studied [10]- [12]. More recently, some groups have begun investigating ways to counteract systematic variations within the fabricated PUFs by adding compensation hardware to the PUF [13], [14].…”

Section: Introductionmentioning

confidence: 98%

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Improving the Quality of Delay-Based PUFs via Optical Proximity Correction

Forte

Srivastava

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Silicon physically unclonable functions (PUFs) are circuits that exploit modern manufacturing variations to generate unique signatures for chip authentication and cryptographic key generation. Existing research has focused on improving PUF quality at architectural or design levels, but has ignored opportunities available during fabrication, which is the source of systematic and random variation in (ICs)/PUFs. For typical ICs (where security is not a concern), optical proximity correction (OPC) is used to suppress both these types of variations. However, several prior works have shown that only systematic variations negatively impact PUF quality and random variations are beneficial for PUFs. In this paper, we propose two PUF-aware OPC cost functions: 1) P-OPC generates a PUF lithography mask that increases all variations in PUF circuitry (the opposite of state-of-the-art OPC), and 2) SVC-OPC generates mask patterns that reduce the systematic variation found in PUFs for better quality. Simulation results for ring oscillator (RO) PUFs show that the proposed techniques can improve PUF signature quality compared to current state-of-the-art OPC.

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Section: Discussionmentioning

confidence: 86%

Section: Introductionmentioning

confidence: 98%

Improving the Quality of Delay-Based PUFs via Optical Proximity Correction

Forte

Srivastava

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Around 100,000 challenge-response pairs were generated under different operating conditions (0 − 75 • C and ±10%V dd ) for determining ΔT min distribution. There exist several circuit-and system-level techniques to improve the reliability of PUF circuits [19], [20]. Some of the common methods include error-correction codes, feedback based control (supply voltage, body-biasing etc.…”

Section: A Reliability Monitorsmentioning

confidence: 99%

Post-Silicon Validation and Calibration of Hardware Security Primitives

Suresh

Kumar

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are gaining significant importance in the field of hardware security. These cryptographic primitives harness randomness from IC fabrication process and on-chip noise respectively; necessitating unconventional post-Silicon (Si) validation techniques. In this work, we present a brief survey of post-Si validation techniques for PUFs and TRNGs, highlighting the importance of testing PUFs resilience against novel attacks and monitoring bias in TRNGs. We also propose novel techniques for monitoring PUFs reliability and measuring bias in TRNGs. The proposed techniques do not only facilitate on-chip calibration for hardware security systems, but can also be used as a countermeasure against fault-attacks.

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“…Therefore, these experimental results demonstrate a good overall reproducibility of CF-ROPUF sample frequencies under varying temperatures and supply voltages. The reliability of our configurable PUF with different types of silicon PUFs that are suitable for FPGA [16], [55], [56] are compared in Table 4. Our CF-ROPUF shows a slightly better average reliability as compared to the other designs.…”

Section: ) Puf Reproducibilitymentioning

confidence: 99%

Enhancing the Performance of Lightweight Configurable PUF for Robust IoT Hardware-Assisted Security

et al. 2021

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Lightweight physical unclonable functions (LPUFs) exploit manufacturing process variations of semiconductor integrated circuits (ICs) to protect IoT-based electronic and smart devices from new cyberattacks. This paper proposes two novel security techniques to enhance the robustness of LPUFs using configurable-based ring oscillator PUFs (CF-ROPUFs). These techniques are the intar-die frequency aware (IFA) approach to improve PUF reliability and the logarithmic gamma function (Ln) technique to enhance PUF randomness. The lightweight CF-ROPUF design is realized on hardware, and data samples are collected under varying temperatures and supply voltages over a population of 30 Spartan-3E FP-GAs.Experimental results of the IFA technique in terms of average Hamming Weight (HM) demonstrate that the percentage of the reliable RO sample frequencies PUF output is 98.5%. For the analysis, PUF reliability is evaluated in terms of accuracy, repeatability, and reproducibility, which are the international organization for Standardization (ISO) standards. The results indicate that the RO samples are accurately measured from the CF-ROPUFs mapped in all the chips. After using the proposed 1-out-of-r coding algorithm, the results demonstrate high average repeatability of 98.2% and a magnified average reproducibility of 99.63%. It is also shown that our CF-ROPUF design is immune from accelerated aging impacts reliability issues. Statistical results show thatLnenhances the normality and mitigates the negative impacts of the systematic process variations on RO sample frequencies. Randomness results show that CF-ROPUF binary response bits can successfully pass the 15 NIST test suites for true randomness with an enhanced percentage, 93.3%, with the application of the 1-out-of-r coding INDEX TERMS Lightweight hardware security, configurable ROPUF, PUF reliability, PUF aging, ISO standards.

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On improving reliability of delay based Physically Unclonable Functions under temperature variations

Cited by 27 publications

References 21 publications

Improving the Quality of Delay-Based PUFs via Optical Proximity Correction

Improving the Quality of Delay-Based PUFs via Optical Proximity Correction

Post-Silicon Validation and Calibration of Hardware Security Primitives

Enhancing the Performance of Lightweight Configurable PUF for Robust IoT Hardware-Assisted Security

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