High-Performance Hexagonal Tellurium Thin-Film Transistor Using Tellurium Oxide as a Crystallization Retarder

Kim, Taikyu; Choi, Cheol Hee; Kim, Se Eun; Kim, Jeong‐Kyu; Jang, Jaeman; Choi, Seung-Chan; Noh, Jiyong; Park, Kwon‐Shik; Kim, Jeom‐Jae; Yoon, Soo‐Young; Jeong, Jae Kyeong

doi:10.1109/led.2022.3230705

Cited by 8 publications

(4 citation statements)

References 24 publications

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“…Nevertheless, this use is confined to small- and/or medium-area devices due to the intricate process flow, inhomogeneity from the grain boundary and challenges in upscaling mass production 16 . Extensive efforts have been directed towards exploring organic compounds 17 , 18 , metal halides 19 – 22 and low-dimensional nanomaterials 23 – 29 as p-type semiconductors for transistors. However, these materials show optimal performance only in crystallized form and they come with intrinsic limitations such as low stability, complex synthesis processes, large-area non-uniformity and a lack of industrial compatibility.…”

Section: Mainmentioning

confidence: 99%

Selenium-alloyed tellurium oxide for amorphous p-channel transistors

Liu,

Kim,

Kim

et al. 2024

Nature

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Compared to polycrystalline semiconductors, amorphous semiconductors offer inherent cost-effective, simple and uniform manufacturing. Traditional amorphous hydrogenated Si falls short in electrical properties, necessitating the exploration of new materials. The creation of high-mobility amorphous n-type metal oxides, such as a-InGaZnO (ref. 1), and their integration into thin-film transistors (TFTs) have propelled advancements in modern large-area electronics and new-generation displays2–8. However, finding comparable p-type counterparts poses notable challenges, impeding the progress of complementary metal–oxide–semiconductor technology and integrated circuits9–11. Here we introduce a pioneering design strategy for amorphous p-type semiconductors, incorporating high-mobility tellurium within an amorphous tellurium suboxide matrix, and demonstrate its use in high-performance, stable p-channel TFTs and complementary circuits. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p-orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of around 15 cm2 V−1 s−1 and on/off current ratios of 106–107, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient ageing. This study represents a crucial stride towards establishing commercially viable amorphous p-channel TFT technology and complementary electronics in a low-cost and industry-compatible manner.

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Section: Mainmentioning

confidence: 99%

Selenium-alloyed tellurium oxide for amorphous p-channel transistors

Liu,

Kim,

Kim

et al. 2024

Nature

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“…Moreover, achieving a well-crystalline-oriented Te film continuously grown with a few nm thickness over a 4-in. scale inevitably requires extraordinary or complex processes, such as evaporation at cryogenic temperature, , Al 2 O 3 encapsulation, , and chemical surface treatment, owing to its low crystallization temperature. ,, Overcoming these drawbacks is essential for the practical application and commercialization of Te-based pTFT to ensure processability.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, a new class of low-dimensional material, Te, has been intensively studied as a channel material for pTFT. − Te atoms are covalently bonded with the two nearest atoms, constructing one-dimensional (1D) helical chains along the [001] direction. Each 1D helical chain is bonded by van der Waals interaction, forming hexagonal crystal arrays. , The band gap ( E g ) of the Te film can be continuously modulated from 0.35 to 1.3 eV with the reduction in film thickness due to the quantum confinement effect. , To achieve an E g over 0.7 eV, necessary for a TFT channel layer to ensure I off , the Te film must be less than 10 nm thick. − However, uniformly depositing a few nanometer-thin Te film is technically challenging through conventional physical and chemical vapor deposition processes that use an island growth mechanism. Moreover, achieving a well-crystalline-oriented Te film continuously grown with a few nm thickness over a 4-in.…”

Section: Introductionmentioning

confidence: 99%

Promotion of Processability in a p-Type Thin-Film Transistor Using a Se–Te Alloying Channel Layer

Choi,

Nam,

Kim

et al. 2024

ACS Appl. Mater. Interfaces

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p-type thin-film transistors (pTFTs) have proven to be a significant impediment to advancing electronics beyond traditional Si-based technology. A recent study suggests that a thin and highly crystalline Te layer shows promise as a channel for high-performance pTFTs. However, achieving this still requires specific conditions, such as a cryogenic growth temperature and an extremely thin channel thickness on the order of a few nanometers. These conditions critically limit the practical feasibility of the fabrication process. Here, we report a high-performance pTFT incorporating a 60-nm-thick highly crystalline Se−Te alloyed channel layer, produced using pulsed laser ablation at room temperature. The Se 0.5 Te 0.5 alloy system enhances crystalline temperature and widens the band gap compared to a pure Te channel. Consequently, this approach results in a field-effect mobility of 3 cm 2 /V•s, with an on/off current ratio of 3 × 10 5 , a subthreshold slope of 2.1 V/decade, and a turn-on voltage of 6.5 V, achieved through conventional annealing at 250 °C. To demonstrate its applicability in complementary circuit applications, we integrate a complementary-type inverter using a p-type Se 0.5 Te 0.5 TFT and an n-type Al-doped InZnSnO, demonstrating a high voltage gain of 12 and a low static power consumption of 17 nW. This suggests that the Se−Te alloyed channel approach paves the way to a more straightforward and cost-effective process for Te-based pTFT devices and their applications.

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“…In addition to TMD materials, oxide semiconductor-based TFTs also have been developed as n-type TFTs, where recent works have shown the amorphous indium–gallium-zinc-oxide TFTs via low-temperature fabrication and other oxide semiconductor-based TFTs with solution-driven gate dielectrics. – Considering that p-channel TFT is highly needed to implement complementary metal-oxide semiconductor logic circuits, a new class of p-type channels is required to develop high-performance devices with a low processing temperature. In recent years, tellurium (Te), a group IV quasi-2D material, has been considered as an advantageous p-type elemental semiconductor for various applications in nanoelectronics, optoelectronics, and energy harvesting devices. – Te has an anisotropic structure, where the Te atoms are covalently bonded with two neighbor atoms in a triangular helical chain, which is stacked together in a hexagonal array through weak van der Waals forces; thus, the naturally terminated surfaces with no dangling bonds can form a clean interface, and high-performance Te-based devices with high hole mobility and air stability can be achieved. – Based on the unique structure of Te that enables the implementation of high-performance p-type TFT, many groups have made efforts to develop growth techniques for high-quality Te thin films, including thermal evaporation-based deposition, , molecular beam epitaxy, , and the liquid-phase process of Te nanosheets. , Among those, the growth of Te thin films with maximum grain size was mostly achieved by evaporation at cryogenic temperature, according to the previous reports, , where the grain size of Te thin film and its carrier transport depend on the deposition temperature and nucleation during thermal evaporation. Thus, it is highly demanded to develop a new approach for the synthesis of Te thin films at room temperature to demonstrate the practical use of Te TFT with high performance and excellent stability.…”

Section: Introductionmentioning

confidence: 99%

Synthesis of a Tellurium Semiconductor with an Organic–Inorganic Hybrid Passivation Layer for High-Performance p-Type Thin Film Transistors

Lim,

Kim,

Park

et al. 2023

ACS Appl. Electron. Mater.

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Development of high-performance p-channel devices is in high demand for implementing complementary metal-oxide semiconductor logic circuits. In this study, we propose a synthetic approach to high-performance p-type tellurium (Te) thin-film transistors (TFTs) passivated with an organic–inorganic hybrid passivation layer. A quasi-two-dimensional Te channel is synthesized by the sputtering system at room temperature, and an organic–inorganic hybrid passivation layer is formed via infiltration of the synthesis process, including diffusion and infiltration of inorganic Al2O3 into an SU-8 polymeric template, resulting in a high-performance p-type Te TFT with a field-effect mobility of 13.6 cm2/(V s), a subthreshold swing of 6.15 V/decade, and a current on–off ratio of 1.35 × 104. The synergistic effect of Al2O3 and SU-8 is systematically analyzed by implementing devices with hybrid passivation layers, enabling a significant improvement in the device performance compared with that of the device passivated with a single Al2O3 layer. Based on the chemical states and Raman response of the proposed structure, the reduction of oxidative Te states and the strain-induced shifts of the Raman modes are shown to attribute to the compensation for the thermal expansion mismatch and the decrease in the strain-induced damage, leading to enhanced device performance with excellent long-term stability over 70 days in the air. Thus, our work demonstrates the great potential of high-performance p-type Te TFTs for future electronic applications.

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High-Performance Hexagonal Tellurium Thin-Film Transistor Using Tellurium Oxide as a Crystallization Retarder

Cited by 8 publications

References 24 publications

Selenium-alloyed tellurium oxide for amorphous p-channel transistors

Selenium-alloyed tellurium oxide for amorphous p-channel transistors

Promotion of Processability in a p-Type Thin-Film Transistor Using a Se–Te Alloying Channel Layer

Synthesis of a Tellurium Semiconductor with an Organic–Inorganic Hybrid Passivation Layer for High-Performance p-Type Thin Film Transistors

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