High-performance implementation of convolution on multiple field-programmable gate array boards using number theoretic transforms defined over the Eisenstein residue number system

Digital Signal Processing with Field Programmable Gate Arrays

“…2. The ERNS FFT, from Meyer-Bäse et al [174], uses the Rader algorithm in combination with the number theoretic transform, which will also be discussed in Chap. 7.1.…”

“…7.1a. In addition this allows a simplified bus structure if a multi-FPGA implementation [174] is used. • Fermat NTTs with M = 2 (2 t ) + 1 have a power-of-two length N = 2 t , and can therefore be implemented with the usual Cooley-Tukey radix-2-type FFT algorithm, which we discussed in Chap.…”

“…A Xilinx XC4K multi-FPGA board has been used to implement this design, as reported in [174]. A Xilinx XC4K multi-FPGA board has been used to implement this design, as reported in [174].…”