High-Performance Low-Power Carry Speculative Addition With Variable Latency

Lin, Iuon-Chang; Yi-ming, Yang; Lin, Cheng-Chian

doi:10.1109/tvlsi.2014.2355217

Cited by 56 publications

(11 citation statements)

References 15 publications

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“…Hence, the carry propagation chain is truncated into shorter segments. Segmentation is also utilized in [1,5,8,10,12,25], but their carry inputs for each sub-adder are selected differently. This type of adder is referred to as a carry select adder.…”

Section: Reviewmentioning

confidence: 99%

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A Comparative Review and Evaluation of Approximate Adders

Jiang

Han

Lombardi

2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

158

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As an important arithmetic module, the adder plays a key role in determining the speed and power consumption of a digital signal processing (DSP) system. The demands of high speed and power efficiency as well as the fault tolerance nature of some applications have promoted the development of approximate adders. This paper reviews current approximate adder designs and provides a comparative evaluation in terms of both error and circuit characteristics. Simulation results show that the equal segmentation adder (ESA) is the most hardware-efficient design, but it has the lowest accuracy in terms of error rate (ER) and mean relative error distance (MRED). The error-tolerant adder type II (ETAII), the speculative carry select adder (SCSA) and the accuracyconfigurable approximate adder (ACAA) are equally accurate (provided that the same parameters are used), however ETATII incurs the lowest power-delay-product (PDP) among them. The almost correct adder (ACA) is the most power consuming scheme with a moderate accuracy. The lower-part-OR adder (LOA) is the slowest, but it is highly efficient in power dissipation.

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Section: Reviewmentioning

confidence: 99%

“…Different from SCSA, the carry speculative adder (CSPA) in [12] contains one sum generator, two internal carry generators (one with carry-0 and one with carry-1) and one carry predictor in each block. The output of the i th carry predictor is used to select carry signals for the (i + 1) th sum generator.…”

Section: The Carry Speculative Addermentioning

confidence: 99%

A Comparative Review and Evaluation of Approximate Adders

Jiang

Han

Lombardi

2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

158

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show abstract

“…2) For many specific applications, the inputs are more or less close to uniform distribution. 3) A number of previous works ( [2], [5], [6], [7], [10], [11], [13], [14]) in analyzing the error statistics of approximate adders also make this assumption. Under the assumption of uniform distribution, we first show an accurate and efficient method to calculate the error rate.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Method for Calculating the Error Statistics of Block-Based Approximate Adders

et al. 2019

IEEE Trans. Comput.

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Adders are key building blocks of many error-tolerant applications. Leveraging the application-level error tolerance, a number of approximate adders were proposed recently. Many of them belong to the category of block-based approximate adders. For approximate circuits, besides normal metrics such as area and delay, another important metric is the error measurement. Given the popularity of block-based approximate adders, in this work, we propose an accurate and efficient method to obtain the error statistics of these adders. We first show how to calculate the error rates. Then, we demonstrate an approach to get the exact error distribution, which can be used to calculate other error characteristics, such as mean error distance and mean square error.

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“…The block‐based adders demonstrate better in terms of speed compared to approximate LSB adders. Speculative adders proposed in [17] exhibit reduced critical path delays to sub‐logarithmic level by exploiting the trade‐off between reliability and performance. Speculative adders combine speculation with error correction to achieve high accuracy and low area overhead over traditional approximate designs.…”

Section: Introduction and Literature Reviewmentioning

confidence: 99%

Area‐efficient parallel adder with faithful approximation for image and signal processing applications

Palanisamy¹,

Natarajan²,

Sundaram³

2019

IET image process

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Design of low‐power and area‐efficient portable complementary metal–oxide–semiconductor processors for image and signal processing applications demand reduction in transistor switching and count. Adder is the fundamental block of all arithmetic operations performed in processing units. In this study, an error‐tolerant parallel adder with faithful approximation is proposed that can optimise area and accuracy. In the proposed parallel adder, for n bit input and m bit adder block, least n/2m blocks are designed with approximate logic using carry by‐pass addition algorithm and most n/2m blocks are designed with exact logic using carry select addition algorithm. Least significant approximate part of the adder is designed with either exact full adder (EFA) or fault‐tolerant full adder (FTFA) cells. This confines the maximum error in the proposed‐EFA and proposed‐FTFA designs to be not more than unit bit value with weights 2[(n/2m)−1]m and 2n/2, respectively. Two different FTFA cells are proposed and implemented in the approximate blocks. The synthesis results of the proposed‐EFA, proposed‐FTFA1 and proposed‐FTFA2 designs using Cadence Encounter with 90 nm ASIC technology for n = 16, m = 4 demonstrated an area saving of 22.3, 28.2 and 35%, respectively, when compared to the conventional counterpart.

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High-Performance Low-Power Carry Speculative Addition With Variable Latency

Cited by 56 publications

References 15 publications

A Comparative Review and Evaluation of Approximate Adders

A Comparative Review and Evaluation of Approximate Adders

An Efficient Method for Calculating the Error Statistics of Block-Based Approximate Adders

Area‐efficient parallel adder with faithful approximation for image and signal processing applications

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