High-performance, low-power resonant clocking

Abstract

Clock distribution networks consume a significant portion of onchip power. Traditional buffered clock distribution power is limited by frequency, capacitance, and activity rates. Resonant clock distributions can reduce this power by "recycling" energy on-chip and reducing the overall clock power. This tutorial introduces recent techniques for distributed-LC, traveling wave, and standing wave resonant clock distributions. In particular, the tutorial discusses the recent developments and open research problems. The tutorial covers both circuits, computer-aided design algorithms and methodologies for resonant clocking.

3.3-mA 2.8-GHz bufferless LC oscillator directly driving a 10-mm on-chip clock distribution line

“…1.2 Previous work Many works have been investigated for low-power resonant clock distribution [4,5,6,7,8,9,10,11,12,13]. A 1.5-GHz bufferless LC oscillator introduced by Mesgarzadeh et al [4,5] achieved an ∼57% lower clock power as compared to a conventional repeater-based LC oscillator.…”