2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) 2010
DOI: 10.1109/csics.2010.5619670
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High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate

Abstract: In this work we present recent results on the direct heterogeneous integration of InP HBTs and Si CMOS on a silicon template wafer or SOLES (Silicon On Lattice Engineered Substrate). InP HBTs whose performance are comparable to HBTs on the native InP substrates have been repeatedly achieved. 100% heterogeneous interconnect yield has been achieved on daisy chain test structures with CMOS-InP HBT spacing (interconnect length) as small as 2.5um. In DARPA COSMOS Phase 1 we designed and fabricated a differential am… Show more

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Cited by 15 publications
(5 citation statements)
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“…The complications of planarizing over large topography in close proximity can limit the co-integration of alternate material between devices in a circuit. For heterogeneous devices and circuits, patterned selective-area-growth (SAG) methods provide a direct and potentially more flexible means to directly integrate disparate materials epitaxially at the fine feature level [1], if defectivity can be managed. One such technique is by means of trench-based epitaxial techniques, which include the well-known Aspect-Ratio-Trapping (ART) of defects [2], [3].…”
Section: Defect and Epitaxy Engineeringmentioning
confidence: 99%
“…The complications of planarizing over large topography in close proximity can limit the co-integration of alternate material between devices in a circuit. For heterogeneous devices and circuits, patterned selective-area-growth (SAG) methods provide a direct and potentially more flexible means to directly integrate disparate materials epitaxially at the fine feature level [1], if defectivity can be managed. One such technique is by means of trench-based epitaxial techniques, which include the well-known Aspect-Ratio-Trapping (ART) of defects [2], [3].…”
Section: Defect and Epitaxy Engineeringmentioning
confidence: 99%
“…This will allow the integration process to take advantage of the high yield of the CMOS BEOL. Examples of completed demonstration circuits are shown in figure 3 (a high-speed InP-Si CMOS differential amplifier [18]-the COSMOS Phase 1 demonstration vehicle containing highspeed InP HBT differential pairs and CMOS current sources and an InP HBT buffer amplifier) and 4 (a high-dynamic-range digital-to-analogue converter (DAC) with over 50 000 CMOS transistors and 1500 InP HBTs) [19]. The DAC was implemented with 180 nm CMOS.…”
Section: (I) Iii-v Bicmos (Inp and Si Cmos)mentioning
confidence: 99%
“…The InP HBT -Si CMOS integrated process (and design kit) has been successfully scaled to 180nm CMOS, 1um emitter InP HBTs, and 200mm diameter SOLES. Using the COSMOS design kit, we designed a low power dissipation (<2.5W), high resolution (14 bit, > 78 dB spur free dynamic range (SFDR)) digital-to-analog converter (DAC) (Figure 6, left) (11,12). DAC3 uses a return to zero (RZ), current steering (Current-Source-Switch or CSS) architecture with on-chip static and dynamic calibration circuitry.…”
Section: Circuit Demonstrationsmentioning
confidence: 99%