We report on a gate-recessed AlGaN/GaN highelectron mobility transistor (HEMT) on a SiC substrate with a record power-gain cutoff frequency (f max). To achieve this high f max , we combined a low-damage gate-recess technology, scaled device geometry, and recessed source/drain ohmic contacts to simultaneously enable minimum short-channel effects (i.e., high output resistance R ds) and very low parasitic resistances. A 60-nm-gate-length HEMT with recessed AlGaN barrier exhibited excellent R ds of 95.7 Ω • mm, R on of 1.1 ∼ 1.2 Ω • mm, and f max of 300 GHz, with a breakdown voltage of ∼20 V. To the authors' knowledge, the obtained f max is the highest reported to date for any nitride transistor. The accuracy of the f max value is verified by small signal modeling based on carefully extracted S-parameters.

Strained transition layers, which are common for heteroepitaxial growth of functional semiconductors on foreign substrates, include high defect densities that impair heat conduction. Here, we measure the thermal resistances of AlN transition layers for GaN on Si and SiC substrates in the temperature range 300 < T < 550 K using time-domain thermoreflectance. We propose a model for the effective resistance of such transition films, which accounts for the coupled effects of phonon scattering on defects and the two interfaces. The data are consistent with this model using point defects at concentrations near 10 20 cm −3 and transmission coefficients based on the diffuse mismatch model. The data can be also described using lower transmission coefficients and eliminating the defects in the AlN. The data and modeling support the hypothesis that point defect scattering in the AlN film dominates the resistance, but may also be consistent with a high presence of near-interfacial defects in the bounding films.

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GaN high electron mobility transistors (HEMTs) were monolithically integrated with silicon CMOS to create a functional current mirror circuit. The integrated circuit was fabricated on 100 mm diameter modified silicon-on-insulator (SOI) wafers incorporating a resistive (111) silicon handle substrate and a lightly doped (100) silicon device layer. In a CMOS-first process, the CMOS was fabricated using the (100) device layer. Subsequently GaN was grown by plasma molecular beam epitaxy in windows on the (111) handle substrate surface without wire growth despite using gallium-rich growth conditions. Transmission lines fabricated on the GaN buffer/SOI wafer exhibited a microwave loss of less than 0.2 dB/mm up to 35 GHz. Direct current measurements on GaN HEMTs yielded a current density of 1.0 A/mm and transconductance of 270 mS/mm. At 10 GHz and a drain bias of 28 V, 1.25 mm long transistors demonstrated a small signal gain of 10.7 dB and a maximum power added efficiency of 53% with a concomitant power of 5.6 W. The silicon and GaN transistors were interconnected to form high yield test interconnect daisy chains and a monolithic current mirror circuit. The CMOS output drain current controlled the GaN transistor quiescent current and consequently the microwave gain.