2010
DOI: 10.1016/j.sse.2009.10.001
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High performance pMOS circuits with silicon-on-glass TFTs

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Cited by 12 publications
(10 citation statements)
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“…It corresponds to a total propagation delay of 2.54 ns/stage. This CMOS propagation delay time is less than 2.61 ns reported for the SiOG PMOS inverter with V DD = 10 V. 8 We also fabricated a dynamic shift register using CMOS SiOG TFTs. Figure 4a shows the schematic of the dynamic shift register.…”
Section: Figure 2amentioning
confidence: 79%
“…It corresponds to a total propagation delay of 2.54 ns/stage. This CMOS propagation delay time is less than 2.61 ns reported for the SiOG PMOS inverter with V DD = 10 V. 8 We also fabricated a dynamic shift register using CMOS SiOG TFTs. Figure 4a shows the schematic of the dynamic shift register.…”
Section: Figure 2amentioning
confidence: 79%
“…V DD and V HIGH of the input signal are both 7.01 V. V SS and V LOW are 0 V. The output load of the measurement circuit has a capacitance of 3 pF and resistance of 1 MΩ. The rise and fall times are 0.4 and 0.7 μs respectivelysignificantly faster than the 2.8 μs and 1.4 μs rise and fall time reported for the PMOS SiOG shift register(7).…”
mentioning
confidence: 86%
“…To fabricate high-performance Si-based TFT on glass substrate, various low-temperature process technologies have been studied. [13][14][15][16][17][18][19][20][21][22][23][24][25] However, in the conventional Si-based TFT process for display application, most of the area of the Si films deposited on the glass substrate (except the regions containing TFTs) is removed by etching. The efficiency of silicon usage (hereafter, material-use efficiency) of silicon is therefore very low.…”
mentioning
confidence: 99%