Low Voltage-Driven CMOS Circuits Based on SiOG

Abstract

The fabrication of the low voltage-driven inverter, ring oscillator, and shift resistor using n-and p-channel thin-film transistors ͑TFTs͒ based on the silicon-on-glass ͑SiOG͒ substrate was studied. The manufacturing process of n-and p-channel TFTs was the same as that of low temperature poly-Si. The field-effect mobilities of n-and p-channel TFTs fabricated in SiOG are 226 and 165 cm 2 /V s, respectively. The TFTs exhibited a symmetric threshold voltage of Ϯ1.1 V and a gate voltage swing of 0.21-0.23 V/dec. The total propagation delay time of the complementary metal oxide semiconductor ͑CMOS͒ inverter was 2.54 ns at a supply voltage of 7 V. In addition, the rise and fall times of the shift register were found to be 0.5 and 0.7 s at a V DD of 7 V, respectively.Low temperature, polycrystalline-silicon ͑LTPS͒ thin-film transistors ͑TFTs͒ on glass continue to generate interest because of their applications in integrated circuits for active-matrix liquid-crystal displays and organic light-emitting diode displays. 1 Sequential lateral solidification 2 and continuous grain silicon, technologies were developed to yield TFTs with higher field-effect mobility compared to the excimer laser-annealed ͑ELA͒ poly-Si TFTs. Unfortunately, grain boundaries remain in these LTPS, which have adverse effects on mobility and performance uniformity, hence making them less ideal for uniform, high speed integrated circuitry.To avoid the grain boundaries in the TFT channel region, several attempts have been made to transfer single-crystalline Si layers to glass substrates, including the Corning silicon-on-glass ͑SiOG͒ substrate. 3 Previous studies comparing p-channel metal oxide semiconductor ͑PMOS͒ circuits built in SiOG and ELA LTPS substrates showed the response time of the circuits built in SiOG to be approximately four times faster. 4,5 Realizing that circuits that employ only p-channel TFTs are plagued by large power consumption, low maximum operation frequency, and large space occupancy, complementary metal oxide semiconductor ͑CMOS͒ circuits became the obvious path to mitigate the PMOS process shortcomings. In this work, the operation of CMOS TFTs fabricated on SiOG is investigated and compared to PMOS results from previous work. ExperimentalThe detailed fabrication process for SiOG appears in a literature by Gadkaree et al. 6 Figure 1 shows the processing steps for the SiOG TFTs; a dry etching was used on the SiOG film to reduce the thickness of Si layer down to 50 nm using plasma composed of a mixture of NF 3 , H 2 , and Cl 2 , as shown in Fig. 1a and b. The variation in the resultant Si film thickness from the NF 3 /Cl 2 /H 2 plasma etch was ϳ1.05%. 7 The Si layer was defined to form active islands by dry etching as shown in Fig. 1c. A 100-nm-thick SiO 2 layer was deposited by plasma-enhanced chemical vapor deposition on SiOG as a gate insulator. Then, 200-nm-thick Mo was deposited and patterned as the gate metal, as shown in Fig. 1d. The p-channel TFT regions are covered with a photoresist, and the self-aligned source and drai...