High performance poly-Si thin film transistors fabricated by self-aligned seed induced lateral crystallization

Abstract

In this study, a low temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) was fabricated by self-aligned silicide seed induced lateral crystallization (SA-SILC). In comparison with a self-aligned metal induced lateral crystallization (SA-MILC) TFT, the SA-SILC TFT showed better electrical properties. In particular, the leakage current was decreased by SA-SILC at high drain voltages. It was found that the Ni rich phase between the channel and drain junction region acted as trapping sites to generate leakage current by thermionic field emission. After applying the SA-SILC process, the p-channel polycrystalline silicon (polySi) TFT exhibited a mobility of 67 cm 2 /V·s, a minimum leakage current of 2.6 × 10 −11 A at VD = −5 V, a subthreshold slope of 0.8 V/dec, and a maximum on/off ratio of 7.0 × 10 6 , together resulting in a highperformance device that surpasses the conventional SA-MILC poly-Si TFT.

Compressive Stressed P-Channel Polycrystalline-Silicon Thin-Film Transistors for High Field-Effect Mobility

“…1(d). The detailed information of the SILC poly-Si TFT is already reported by our group, elsewhere [10]. The compressively stressed poly-Si by SILC showed a tensile stressed glass shown in Fig.…”

“…Finally, the 300-nm-thick SiO 2 and 300-nm-thick Al metals were deposited for inter-layer dielectric (ILD) and metal contacts. The more detailed information of our top-gated poly-Si TFT is reported, elsewhere [10]. The strain-free poly-Si TFT fabricated on Si wafer, showing no thermal mismatch.…”