High-Performance random data lookup for network processing

Abstract

Because the speed degradation and on-chip resources limit large CAM applications on SoCs and FPGAs, Hash-CAM architectures are attractive concepts combining the space efficiency of hashing algorithm and fast lookup character of the CAM for collision resolutions. In proposed Hash-CAM circuit, single and double hashing schemes are explored and compared. It proves that, with parallel CRC circuit and pipeline approach, dual hashing (or multiple hashing) scheme with multiple smaller memory blocks for the hash table is an efficient way to implement Hash-CAM architectures, for medium size lookup table of thousands of entries.