High performance reversed nested Miller frequency compensation

Self Cite

In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A high‐performance CMOS four‐stage amplifier

Zanjani

Asiyabi

Biabanifard³

2019

Self Cite

“…The proposed algorithm was tested on the transfer function of the 3-stage miller compensated op-amp as shown in Figure 4. [19][20][21] First, the circuit was simulated in HSPICE, and then the proposed simplification algorithm simplified the transfer function under MATLAB. Two small-signal transistor models were used ( Figure 5).…”

Section: Resultsmentioning

confidence: 99%

A new pre‐processing algorithm for analog circuit expression and simplification

Chaharmahali

Asadi

Dousti

2016

Self Cite

This paper has proposed a new pre‐processing stage algorithm to enhance the overall performance of current simplification algorithms in analog circuits. This pre‐process stage takes place after the calculation of symbolic transfer function and before the main core of the simplification algorithm. The detailed stages of this pre‐process are completely independent of the main simplification and symbolic transfer function algorithm. As such, the pre‐process algorithm can be easily added to any simplification algorithm to improve the total simplification performance. The use of this command, which is based on the stack decision method, helps the pre‐process algorithm to obtain a high‐process speed. Based on the CPU time simulation results for a transfer function with 139 terms, it is expected to have a total CPU time in the simplification of a 9820 term of about 28 to 30 seconds pulse and 1.2 to 4.9 seconds for the pre‐process algorithm. Finally, a total method, which involves the combination of this pre‐process algorithm with the main simplification algorithm is proposed in, and a CPU time of about 30 to 35 seconds is needed for simplifying a huge transfer function with 9820 terms. The addition of extra pre‐process algorithm to the main simplification algorithm will reduce the total CPU time of simulation from 820 to 35 seconds, indicating a reduction of 95% in the total needed simulation time.

“…Finally, ACBC is known as one of the best techniques for frequency compensation. In this method, the second‐stage gain is increased in high frequency, therefore, improving the overall frequency response of an OTA [9, 14, 16‐35] …”

Section: Introductionmentioning

confidence: 99%

“…In this method, the second-stage gain is increased in high frequency, therefore, improving the overall frequency response of an OTA [9,14,[16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35]. 9,14,[16][17][18][19][20][21][22] In this article, a new compensation technique is proposed. It uses a fully differential feedback path to remove the feedforward path and enhance the frequency response regarding PM and GBW.…”

Section: Introductionmentioning

confidence: 99%

Multistage operational transconductance amplifier frequency compensation technique based on fully differential feedback stage

Zanjani

Khatib

Chabok

2019

In this article, a new configuration of a three-stage Complementary metaloxide-semiconductor (CMOS) operational transconductance amplifier (OTA) isproposed. It removes the feedforward path while simultaneously amplifying the feedback path in the compensation network. Also, the proposed circuit uses only one small compensation capacitor which makes it appropriate regarding die area. The approach behind is demonstrated through a successful design using 0.18-μm CMOS technology. In fact, the simulated OTA shows better performance in comparison with other methods and achieved 20.2 MHz, 82 , and 124 dB as gain-bandwidth product, phase margin, and DC gain, respectively, and consumes 545 μW @ 1.8 V. K E Y W O R D S