High Performance Significance Approximation Error Tolerance Adder for Image Processing Applications

Jothin, R.; Vasanthanayaki, C.

doi:10.1007/s10836-016-5587-z

Cited by 25 publications

(62 citation statements)

References 5 publications

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“…Block diagram of error tolerant carry select adder (ET_ CSLA). 12 AFA, approximate full adder FIGURE 5 Block diagram of significant approximation error tolerant carry select adder (SAET_ CSLA). 12 AFA, approximate full adder;…”

Section: Figurementioning

confidence: 99%

“…From Table 4, it may be noted that the proposed adders LETA and ILETA achieves the reduction in terms of gate count compared to existing ETAs. 12,14 3 RESULT AND ANALYSIS…”

Section: Iletamentioning

confidence: 99%

“…Existing approximate full adders, A, approximate full adder (AFA), B, modified full adder (MFA),C, multiplexer based on approximate full adders (MBAFA)…”

Section: Proposed Workmentioning

confidence: 99%

“…A detailed block diagram of the ET_ CSLA is shown in Figure . From Figure , it may be observed that the ET_ CSLA is formulated by using the AFA as a building block. For A 16‐bit ET_ CSLA, it requires 28 AFA and 15 multiplexers.…”

Section: Proposed Workmentioning

confidence: 99%

“…The AFA is designed to reduce the error probability in outputs with two errors in sum signal and error free carry signal. In AFA, the carry signal is generated based on the carry generation circuit.…”

Section: Introductionmentioning

confidence: 99%

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Low power and area efficient error tolerant adder for image processing application

Priyadharshni

Sundaram

2020

Circuit Theory & Apps

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Approximate computing-based arithmetic units are oriented towards reduction in power, delay, and area. Intrinsic error tolerance capability of emerging application domains, like multimedia, Internet of Things (IoT), and image processing provides better opportunities for optimization of approximate arithmetic units. In this paper, a novel 1-bit imprecise full adder (IFA) is proposed with less gate count. Also, two versions of 16-bit error tolerant adders (ETAs), namely a low power and area efficient error tolerant adder (LETA) and improved low power and area efficient error tolerant adder (ILETA), are proposed. In these proposed ETAs, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using an existing modified full adder (MFA) and proposed IFAs, respectively. The proposed and existing ETA adders are implemented using a Verilog hardware description language (HDL) and synthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA) adders exhibit (55%, 50%) reduction in power consumption and achieve significant reduction in area (68%, 61%). Further, in this work, a new performance metric namely power and error product (PEP) is proposed in order to evaluate the approximate adders in terms of power and error metrics. It is found that the proposed ILETA achieves a low PEP of 1.05×10 −5 compared with other ETAs. To study the efficacy of the proposed ETA adders in image processing application, an image blending algorithm is implemented and simulated using MATLAB. From simulation results, it is observed that the proposed ETA adders exhibit a high peak signal-to-noise ratio (PSNR). KEYWORDSapproximate carry select adder, approximate computing, approximate full adder, imprecise full adder, error tolerant adder Int J Circ Theor Appl. 2020;48:696-708. wileyonlinelibrary.com/journal/cta

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Section: Figurementioning

confidence: 99%

“…From Table 4, it may be noted that the proposed adders LETA and ILETA achieves the reduction in terms of gate count compared to existing ETAs. 12,14 3 RESULT AND ANALYSIS…”

Section: Iletamentioning

confidence: 99%

“…Existing approximate full adders, A, approximate full adder (AFA), B, modified full adder (MFA),C, multiplexer based on approximate full adders (MBAFA)…”

Section: Proposed Workmentioning

confidence: 99%

Section: Proposed Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low power and area efficient error tolerant adder for image processing application

Priyadharshni

Sundaram

2020

Circuit Theory & Apps

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An error efficient and low complexity approximate multi‐bit adder for image processing applications

Priyadharshni

Gupta

Kumar

et al. 2021

Circuit Theory & Apps

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Approximate computing-based hardware is directed towards reduction in area and power consumption; it finds better suitability in various image processing applications. In order to achieve low complexity, approximate techniques are applied in the arithmetic units which provide promising results in enhancing the performance of DSP processors with optimal degradation on its accuracy.In this paper, two approximate full adder designs are proposed, namely, the first design as proposed approximate full adder 1 (PAA 1 ) and the second design as proposed approximate full adder 2 (PAA 2 ). In both the designs, the approximation on the Boolean expressions is carried out to reduce the hardware complexity with the significant tolerance on the error rate. Also, a multi-bit approximate carry select adder is proposed with the utilization of PAA 1 and PAA 2 , respectively. The performance of the proposed adders is analyzed in terms of parameters like gate count, structural synthesis, error, and also in terms of image metrics. The proposed and existing designs are synthesized using Synopsys Design Compiler with TSMC 65 nm technology for better comparison. Synthesis results indicate that the proposed 16-bit approximate carry select adder (CSLA) shows a significant reduction of 58% in area delay product and 70% in power delay product, in comparison with the conventional CSLA. The image metrics results also validate that the proposed adder with highest peak signal-to-noise ratio is highly adoptable for image processing applications.

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High-Performance Carry Select Adders

Jothin

Sreelatha

Ahilan

et al. 2021

Circuits Syst Signal Process

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High Performance Significance Approximation Error Tolerance Adder for Image Processing Applications

Cited by 25 publications

References 5 publications

Low power and area efficient error tolerant adder for image processing application

Low power and area efficient error tolerant adder for image processing application

An error efficient and low complexity approximate multi‐bit adder for image processing applications

High-Performance Carry Select Adders

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