High performance silicon-based substrate using buried PN junctions towards RF applications

Moulin, Maxime; Rack, Martin; Fache, T.; Chalupa, Zdenek; Plantier, Christophe; Morand, Y.; Lacord, J.; Allibert, F.; Gaillard, F.; Lugo, J.; Hutin, Louis; Raskin, Jean‐Pierre

doi:10.1109/eurosoi-ulis53016.2021.9560171

Cited by 6 publications

(4 citation statements)

References 8 publications

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“…Thus, the proportion of depleted volume in the interfacial silicon layer (P-and N-doped regions) for those samples was 7.4% (160 nm/2.16 µm). More recently, the concept has been tested with a more advanced fabrication process (180 nm photolithography resolution) at CEA-Leti enabling a higher density of depletion junctions (47%) to be defined in a given space, thereby increasing the substrate impedance even further to produce even better RF results [43].…”

Section: Frequency [Ghz]mentioning

confidence: 99%

Fully Depleted SOI Technology for Millimeter-Wave Integrated Circuits

Raskin

2022

IEEE J. Electron Devices Soc.

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Performances of high-frequency integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted (FD) SOI MOSFET is foreseen as one of the most promising candidates for the development of future lower power wireless communication systems operating in the millimeter-wave range. The high frequency performances of FD SOI transistors are presented at room but also at cryogenic and high temperature. Recently published results for FD SOI switches and low noise amplifiers are summarized. And finally, the potential interest and challenges to move from standard to high resistivity FD SOI substrates are discussed.

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Section: Frequency [Ghz]mentioning

confidence: 99%

Fully Depleted SOI Technology for Millimeter-Wave Integrated Circuits

Raskin

2022

IEEE J. Electron Devices Soc.

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“…This is due to the constantly decreasing effective resistivity with frequency. The phenomenon is described more extensively in [20,21,22]. TCAD simulations using ATLAS software from Silvaco [23] were realized.…”

Section: B Small-signal Characterizationmentioning

confidence: 99%

“…Having shorter pitches between each PN junction, and consequently a larger depletion regions density underneath the BOX, the substrate effective resistivity should increase even more over a wider frequency band [24]. Doses of P and N doping were adapted from [20], where a maximum of effective resistivity is obtained for 2.10 13 cm −2 . The main design trade-off in terms of doses is between the size of depletion regions and robustness to oxide charges Q ox .…”

Section: B Small-signal Characterizationmentioning

confidence: 99%

“…Compared to the others, DP is a medium substrate in terms of performances but has an easy fabrication as it only uses standard doping implantation process steps. It is a recent prototype so its performances can be greatly improved through additional research, for instance by adapting the process reducing the PN-junction pattern size, which was done by [20] and in this article. PSi exhibits effective resistivity comparable to TR and has the lowest insertion losses and best linearity.…”

Section: Large-signal Characterizationmentioning

confidence: 99%

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