High-Performance SLS Nanowire TFTs With Dual-Gate Structure

Kang, Tsung-Kuei

doi:10.1109/ted.2013.2261694

Cited by 6 publications

(2 citation statements)

References 31 publications

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“…Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been widely developed for various TFT applications including system-on-panel technology, nonvolatile memory, and active-matrix organic light-emitting diode technology. [1][2][3][4][5][6] Compared with amorphous silicon TFTs, LTPS TFTs have demonstrated higher mobility, [7][8][9] which could be further improved by adopting advanced fabrication techniques such as the use of a high-k material, patterning, and various structures. [10][11][12][13][14][15][16][17][18] However, as TFTs have been scaled down, the adverse effects of the inherent grain boundary (GB) on electrical characteristics and their reliability have become significant.…”

Section: Introductionmentioning

confidence: 99%

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

Lee

Jin

et al. 2018

Jpn. J. Appl. Phys.

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The effects of geometrical parameters on the electrical characteristics of network-channel low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) were investigated. The grain boundary and interface trap densities were also extracted using parameters such as hole-to-hole distance, hole-branch top width, effective channel width, and area filling factor (AF). It was found that the electrical characteristics were largely dependent on AF, mainly owing to reduced trap densities. However, excessive hole formation in the network-channel structure was found to increase channel resistance and decrease drain current. These results suggest that, for a given footprint device area, denser hole patterns are preferred for achieving better electrical characteristics in novel network-channel LTPS TFTs.

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Section: Introductionmentioning

confidence: 99%

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

Lee

Jin

et al. 2018

Jpn. J. Appl. Phys.

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“…Under these circumstances, technology computer-aided design (TCAD) simulation is necessary to systematically study and explore the physical mechanisms underlying the dependence of the TFT performance on the UR offset. In addition to conventional single-gate poly-Si TFTs, dual-gate poly-Si TFTs have also been widely used in display technology [16,17]. Although the UR offset frequently occurs in poly-Si TFTs, the influence of the UR offset especially on the performance of dual-gate poly-Si TFTs is seldom studied in literature.…”

Section: Introductionmentioning

confidence: 99%

Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

Hsu¹,

Chen²

2019

Semicond. Sci. Technol.

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In this paper, electrical characteristics of dual-gate polycrystalline silicon (poly-Si) thin film transistors (TFTs) with different undoped region (UR) offsets are investigated. Performance degradation of the poly-Si TFT is dependent on the offset value, offset direction, and offset location. In addition, the degradation is also dependent on the applied drain bias. Significant performance deterioration is observed when the offset is larger than ±0.4 μm. Even an offset in an individual UR can cause the degradation. At a low drain bias of −0.1 V, the degradation is independent on the direction and the location of the offset. When the drain bias increases to −10 V, the performance degradation of the TFT with the positive UR offset significantly reduces. The physical mechanisms underlying the performance variation are studied by analyzing the energy band diagrams, carrier concentration distributions, and electric field distributions.

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A Subtractive Feedforward Controller Based on Symmetrical Components Decomposition for DFIG Under Balanced and Unbalanced Loads in Weak Grids

2016

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High-Performance SLS Nanowire TFTs With Dual-Gate Structure

Cited by 6 publications

References 31 publications

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

A Subtractive Feedforward Controller Based on Symmetrical Components Decomposition for DFIG Under Balanced and Unbalanced Loads in Weak Grids

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