High Performance Ultra Low-k (k=2.0/keff=2.4)/Cu Dual-Damascene Interconnect Technology with Self-Formed MnSixOy Barrier Layer for 32 nm-node

Abstract

In order to realize the effective dielectric constant (k eff)=2.4 for 32 nm-node copper(Cu) dual-damascene(DD) interconnects, a spin-on-dielectric(SOD) SiOC (k=2.0) as the inter-level dielectric and plasma-induced damage restoration treatment were successfully demonstrated. It was obtained that good via resistance and stress-induced voiding (SiV) reliability. In addition, CoW-cap and thin SiC (k=3.5) and dual hard mask process using a metal layer was proposed to reduce the capacitance of dielectric diffusion barrier and protection layers in hybrid(PAr/SiOC) inter-layer dielectric(ILD) structure. As for the metallization, a self-formed MnSi x O y barrier technology was applied in hybrid ILD structure. Drastic reduction of via resistance and excellent electromigration and SiV performance were obtained for the first time in hybrid ILD structure.

Process Technology for Copper Interconnects

“…Another method to improve the electromigration lifetime is to dope the Cu with impurities such as Al [135,136], Ag [137], or Mn [138][139][140]. The dopants are typically introduced into the Cu seed layer (Figure 8.21H-K).…”

Low‐kMaterials: Recent Advances

“…This observation was utilized in hybrid integration approaches, which utilize a twolayer ILD comprised of an organosilicate layer at the via level and an organic polymer layer at the trench level [8,[123][124][125]. Although this approach limits plasma damage mainly to the via level (top and sidewall surfaces), it complicates the integration approach.…”

Growth of Ti-Based Interface Layer in Cu(Ti)/Glass Samples

“…Extensive efforts have been made to improve these Cu-related issues, for example, developing processes for production of Cu/metal bilayers such as Cu/Co, 6) Cu/ Mo, 7) Cu/Ti, 8) and Cu alloys such as Cu(Cr) 9) and Cu(In). 10,11) Similarly, Cu alloys such as Cu(Ti) [12][13][14][15] and Cu(Mn) 16,17) were investigated to prepare a thin barrier layer on dielectric/Si substrates for ultra-large scale integrated devices, leading to low resistivity and high adhesion. Supersaturated Cu(Ti) alloy films deposited on dielectric layers such as SiO 2 , SiN, SiCO, SiCN, and SiOCH with low dielectric constants (low-k) were annealed at elevated temperatures, and thin Ti-rich layers were formed at the film surface and interface between the film and all the dielectric layers.…”