High-Performance Uniaxially Strained SiGe-on-Insulator pMOSFETs Fabricated by Lateral-Strain-Relaxation Technique

Irisawa, Toshifumi; Numata, T.; Tezuka, T.; Usuda, Koji; Hirashita, Hiroyuki; Sugiyama, N.; Toyoda, Eiji; Takagi, Shinichi

doi:10.1109/ted.2006.884078

Cited by 47 publications

(34 citation statements)

References 16 publications

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“…SiGe has been suggested as the channel material of next generation FETs, because the both mobilities of electrons and holes in SiGe are higher than those in Si. Furthermore, the strain induction in SiGe is considered effective for improving electrical properties of SiGe FETs in the same way as strained Si [38][39][40][41]. The nondiagonal stress components, shear stress components, were measured by analyzing the dependence of Raman spectra on the relative polarization direction between sample orientation and electrical fields of incident and scattered light.…”

Section: Introductionmentioning

confidence: 99%

Stress Measurements in Si and SiGe by Liquid-Immersion Raman Spectroscopy

Kosemura¹,

Tomita²,

Usuda³

et al. 2012

Advanced Aspects of Spectroscopy

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Section: Introductionmentioning

confidence: 99%

Stress Measurements in Si and SiGe by Liquid-Immersion Raman Spectroscopy

Kosemura¹,

Tomita²,

Usuda³

et al. 2012

Advanced Aspects of Spectroscopy

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“…The lateral strain relaxation technique is proposed for this purpose. 88 Preserving the strain along the channel direction while relaxing it along the width direction is the key to this technique. Moreover, the elastic strain relaxation from pattern edges effectively suppresses dislocation nucleation.…”

Section: Sige Channelmentioning

confidence: 99%

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song

Zhou

et al. 2011

Journal of Elec Materi

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The aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal-oxide-semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/ drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new highmobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III-V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.

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“…From this viewpoint, the combination of the global and local strain technologies is promising for optimizing the strain configuration. We have proposed and demonstrated a novel technique to provide uniform and high uni-axial strain, applicable to ultra short channel and multi-gate MOSFETs, through the combination of bi-axial strain structures and lateral strain relaxation [7][8][9][10]. A unique feature of this device is the co-existence of global strain and uniaxial compressive strain, which is advantageous from the viewpoints of both the performance and the robustness against the size variation.…”

Section: Uniaxially-strained Cmos By Combining Global Strain Substratmentioning

confidence: 99%

High mobility channel CMOS technologies for realizing high performance LSI's

Takagi

2009

2009 IEEE Custom Integrated Circuits Conference

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Saturation of CMOS performance has been evident in the present 45/32 nm technology node, because of a variety of physical limitations on the miniaturization. Thus, channel engineering, including the enhancement of drive current due to high mobility channel materials and with robustness against short channel effects and characteristic variation due to multi-gate structures, has currently been recognized as mandatory for high performance CMOS. In this paper, we report our approaches to further improvement of MOSFETs by using strained-Si, SiGe, Ge and III-V semiconductor channels on the Si CMOS platform with an emphasis on the combination of ultra-thin body and multi-gate structures. IntroductionThe device scaling concept, which can lead to the increase in both the switching speed and the number density of MOSFETs under reasonable power consumption, had been the main guiding principle of the MOS device engineering over these thirty years. It has been recognized, however, below 32 nm technology node that this conventional device scaling has confronted the difficulty that the three main indices associated with MOSFET performance, on-current, power consumption and short channel effects, have the trade-off relationship with each other, owing to several physical and essential limitations directly related to the device miniaturization, such as tunneling current, mobility reduction, source/drain resistance, inversion-layer capacitance and Sub-threshold slope.Fig. 1 Schematic log I ds -V g characteristics to show the factor affecting power consumption.Fig. 1 shows a schematic Id-Vg curve of MOSFETs.Here, the power consumption, P consum , and the on current, I on , can be roughly described [1] bywhere a, f, C load , I 0 , S, I leak , N s , C g and υ are a constant value, the operating frequency, the load capacitance, the drain current at V g of V th , the Sub-threshold slope, the total leakage current including gate and junction leakages, the induced surface carrier concentration in the channel, the gate capacitance and the velocity near the source region, respectively. In order to realize low power MOSFETs, lower V dd , higher V th , smaller S (higher immunity to short channel effects) and lower I leak are necessary. However, these requirements clearly conflict with high I on , which is still important for signal processing. Also, these requirements pose severe trade-off relationship on choosing device parameters like gate oxides thickness, T ox , substrate impurity concentration, N sub , meaning that it is physically difficult to further improve the performance and power consumption under the conventional Si CMOS scheme. Source Engineering Gate Stack Engineering metal gate high k Channel Engineering SOI Strained Si, Ge, III-V Back gate, Fin Structure, Double gate, Nano-wire etc. Mobility, velocity, ballistic transport Carrier injection velocity Ultra-shallow junction, source resistance, metal S/D Suppression of SCE EOT Inversion-layer thickness Steep impurity profileFig. 2 Schematic diagram of three types of device enginee...

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High-Performance Uniaxially Strained SiGe-on-Insulator pMOSFETs Fabricated by Lateral-Strain-Relaxation Technique

Cited by 47 publications

References 16 publications

Stress Measurements in Si and SiGe by Liquid-Immersion Raman Spectroscopy

Stress Measurements in Si and SiGe by Liquid-Immersion Raman Spectroscopy

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

High mobility channel CMOS technologies for realizing high performance LSI's

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