High-Power LiNbO₃ Domain-Wall Nanodevices

Abstract

Wide band gap semiconductors keep on pushing the limits of power electronic devices to higher switching speeds and higher operating temperatures, including diodes and transistors on low-cost Si substrates. Alternatively, erasable conducting walls created within ferroelectric single-crystal films integrated on the Si platform have emerged as a promising gateway to adaptive nanoelectronics in sufficient output power, where the repetitive creation of highly charged domain walls (DWs) is particularly important to increase the wall current density. Here, we observe large conduction of the head-to-head DW at an optimized inclination angle of 15° within a LiNbO3 single crystal that is 3–4 orders of magnitude higher than that of the tail-to-tail DW. The wall conduction is diode-like with a linear current density of higher than 1 mA/μm and an on/off ratio of larger than 106 under the application of a repetitive switching voltage pulse in time less than 10 ns and an endurance number of higher than 105. The high-power diodes can not only perform direct data processing in high-density nonvolatile DW memories in fast operation speeds and low-energy consumption but also function as sensors in compact electromechanical systems, selectors in phase-change memory and resistive random-access memory, and half-wave/full-wave rectifiers in modern nanocircuits in dimensions approaching the thickness of the depletion layer below which the tradition p–n junction malfunctions.

Ferroelectric Domain Wall Memory and Logic

“…By control of the orientation of switched domain, it is possible to configure the neutral, head-to-head, and tail-to-tail walls, where the head-to-head domain walls will have N-type conduction in contrast to the P-type conduction of the tail-to-tail domain walls. − If put together, these devices can form P–N junctions, which can then be arranged in different combinations to realize comprehensive NPN and PNP functionalities similar to those of the CMOS devices in modern logic and cascade circuits. Such functionality thus can be envisaged from the injection/annihilation of two types of domain walls after changing the local polarization directions appropriately with their polarities that, e.g., can be switched or frozen after high-temperature charge injection …”

“…However, domain wall memory among other emerging resistive random access memories such as phase change memory, magnetoresistive random access memory, and ferroelectric tunnel junctions provides a potential solution. Compared to other approaches/concepts, wall memory offers a combination of low operating voltages, nanoseconds read/write times, high ON/OFF ratios, and up to a billion endurance cycles . In addition, the electronic conduction of the domain wall is tunable, which allows the development of memory-resistance functions suitable for in-memory computing .…”

“…142−144 If put together, these devices can form P−N junctions, which can then be arranged in different combinations to realize comprehensive NPN and PNP functionalities similar to those of the CMOS devices in modern logic and cascade circuits. Such functionality thus can be envisaged from the injection/annihilation of two types of domain walls after changing the local polarization directions appropriately 58 with their polarities that, e.g., can be switched or frozen after high-temperature charge injection. 70 Moreover, the advent of big data has led to a dramatic increase in computational tasks, posing a huge burden to traditional von Neumann system architectures (where computation and storage units are physically separated).…”

“…The transient charged walls lead to high currents of ∼tens of nA and OFF–ON ratios of ≈100 and 3 for two- and three-terminal devices, respectively. Even higher currents in the range of hundreds of nA, needed for the operation of high-speed and high-power devices, , are achieved through control of injected domain wall hierarchy and the relative angle between the applied field and polarization . Taking this approach a step further in mesa-like memory cells, in contact with two side electrodes, fabricated on the surface of a monodomain x -cut LiNbO 3 single crystal thin film bonded to a silicon substrate, the encoded data are read through the creation and annihilation of persistent and transient domain walls (Figure g).…”

Ferroelectric domain wall memory

“…In the past ten years, various prototype DW memory devices have been demonstrated with capacitor geometries as shown in Fig. 2, which have coplanar electrodes, [42][43][44][45][46] nanoislands, [47][48][49] mesa-type cells, [50][51][52][53] and parallel-plate like capacitors in the top and bottom electrodes [54][55][56][57][58][59] among BiFeO 3 (BFO), LiNbO 3 (LNO), BaTiO 3 (BTO) epitaxial thin films, etc. In this article, we classify such novel DW memories with the brief discussion of their working principles, cell structures, performance, and the prospects in the future.…”