High Precision Defect Inspection & Binning

Abstract

Wafer inspection and defect classification have been traditionally done in Fab solely using wafer level data. For processes as 45 nm and beyond, device performance has become very sensitive to process variations that include litho conditions and process-induced pattern fidelity. For example a slight mismatch in process chamber can have a drastic impact to yield. Also evaluation of OPC treatment on wafer is becoming more difficult when subtle pattern failures can be hidden in high volume of defect data. Certain defect type such as incomplete contact hole cannot be detected before etch and the occurrences can be intermittent, making it virtually impossible to detect them using random sampling [1]. In addition, Foundry Fabs need to meet the challenge of fast device characterization and quick ramp. Design-Aware inspection delivers new capability that allows Fabs to characterize device and process with higher dimension that were not possible before using the traditional approaches.

High Precision Defect Inspection & Binning

“…Certain residue defect can accumulate based on local surface tension which has dependency on Design (GDS layout). [3] Also same defect type falling at different location of device can exhibit varying degree of yield impact. For example a Micron scratch defect in a sparse nonactive area will have a different impact as compared to the same defect occurring over contact.…”

Investigation of Plasma Enhanced Chemical Vapor Deposition Chamber Mismatching by Photoluminescence and Raman Spectroscopy

“…Even if the process chambers are from the same equipment supplier and supposedly identical, we often experience difficulty in matching the process results after a lot of process tuning effort. [1][2][3] Process tuning is typically done by matching physical dimensions and apparent physical properties of processed materials on Si wafers (for example; deposition, etching, bulk and surface treatment, annealing etc.). [4][5][6][7][8][9][10][11] In some cases, problematic process chambers cannot be commissioned for device manufacturing, even after process tuning due to unexplained device performance variations of wafers processed in them for undiscovered reasons.…”

“…[4][5][6][7][8][9][10][11] In some cases, problematic process chambers cannot be commissioned for device manufacturing, even after process tuning due to unexplained device performance variations of wafers processed in them for undiscovered reasons. 2,3,12 It takes several iterations of device fabrication and test cycles to figure this out. It can easily take several months and significant resources.…”

“…[4][5][6][7][10][11][12] Electrical performance variations of final devices processed in different process chambers generally determines whether a particular process chamber can be commissioned for device manufacturing, or not. 2,3,12 If we can detect the potential mismatching problems in a process chamber at an early stage and without going through the lengthy device fabrication and test cycles, it would greatly reduce cost and perhaps shorten the process tuning cycle.…”