High precision on-wafer backend capacitor mismatch measurements using a benchtop semiconductor characterization system

A new robust capacitance mis-match measurement for analog/mixed-signal applications

“…The changes in the gate potential will results in equal changes in source potential. Therefore the slope S in a Vf-Vs plot is determined by Cm and Cr as follows: It has accuracy limitation associated with mis-match of the inverter's transistors [4], 3) Floating gate capacitor matching measurement, using an integrated PMOS source follower to sense the midpoint of capacitive DC voltage divider [5]. Its resolution is limited by parasitics and equipment.…”

“…For all practical purpose, 1) Cbgo and Csgo are independent on the voltages of gate, source and bulk, but Cdgo has an impact on the potential of the floating gate node, 2) initial charge on the floating gate is unknown, 3) the voltage difference between gate and source is reduced as drain voltage increases as shown in Fig 2. 0= I(Cr,t) + I(Cm,t) + I(Cdgo,t) + I(Csgo,t) + I(Cbgo,t) (5) Applying I=C x dVldt to Eq. (5) , Eq.…”