High-$Q$ Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA

Sun, Xiao Wei; Dupuis, O.; Linten, Dimitri; Carchon, G.; Soussan, Philippe; Decoutere, Stefaan; Raedt, W. De; Beyne, Eric

doi:10.1109/tadvp.2006.884827

Cited by 29 publications

(11 citation statements)

References 16 publications

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“…1µm InP pHEMT obtained only better input return loss compared to the proposed work but it has low gain, high NF, low output return loss. [3] designed with CMOS technology shows better performance in terms of IRL and ORL but it offers low gain and high NF compared to proposed work. [4] developed with 0.18µm CMOS technology obtained better gain but with a high NF.…”

Section: Fig 3 Gain Of 38 Ghz Ss Monolithic Lnamentioning

confidence: 81%

“…But they obtained a very high NF. Later on SS LNA's are also designed using CMOS technologies [3,4] with relatively low NF. This proposed work used a SSCS configuration with source degenerated with inductor results a very low NF compared to the above technologies.…”

Section: Introductionmentioning

confidence: 99%

“…In the layout diagram the circle shapes represent the spiral inductors and rectangular bars represent the matching networks. This work occupies less chip area compared to[2,3].…”

mentioning

confidence: 99%

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Single Stage 38 GHz LNA using 0.1 μm GaAs HEMT

2019

IJITEE

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Design of a 38 GHz low noise amplifier using a single stage common source (SSCS) with source degenerated with inductor topology with gain of 9 dB and noise figure (NF) of 1.5 dB using 0.1 µm GaAs pHEMT as active device is proposed in this paper. CS with source degenerated with inductor topology of 0.1 µm GaAs pHEMT resulted a very low NF compared to other HEMT technologies as well as other CMOS technologies at this RF range.

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Section: Fig 3 Gain Of 38 Ghz Ss Monolithic Lnamentioning

confidence: 81%

Section: Introductionmentioning

confidence: 99%

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Single Stage 38 GHz LNA using 0.1 μm GaAs HEMT

2019

IJITEE

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“…In CMOS fabrication, the dummy metal (DM) fill required by chemical mechanical polishing (CMP) process must meet the CMOS metal density rules. However, the generation of an eddy current significantly influences the performance of an inductor with underneath DMs [26]. Therefore, a flipped CMOS inductor coupled with underneath metal markedly degrades the -factor and self-inductance [27].…”

Section: Stacked Rfe With Consideration Of Coupling Effectsmentioning

confidence: 99%

Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices

Horng

2014

IEEE Trans. Microwave Theory Techn.

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This paper presents a stacked RF front-end (RFE) package for wideband receiver applications. While having a power consumption of 18 mW, the flipped CMOS chip consisting of a lownoise amplifier and a quadrature down-conversion mixer stacks on a glass integrated passive device (GIPD) substrate, subsequently achieving a noise figure of 2.2-2.8 dB and a conversion gain of 23-25 dB over 1-6 GHz. Moreover, the RFE package uses a GIPD balun with a high common-mode rejection ratio and a post-distortion linearizer in the CMOS mixer, subsequently resulting in an of 57-68 dBm and an of 5.2-3.5 dBm over the entire operating band. This paper also elucidates how coupling between the flipped CMOS chip and GIPD balun affects the RFE linearity. Fabricated with 0.18-m CMOS technology, the flipped CMOS chip is packaged on the GIPD substrate with a footprint area of 1.8 1.8 mm .

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“…[10] The 5GHz and 15GHz VCOs use respectively a 3nH and a 0.6nH WLP inductor without ground shielding resulting in a differential Q factor of respectively 40 and 55. [10] The 5GHz and 15GHz VCOs use respectively a 3nH and a 0.6nH WLP inductor without ground shielding resulting in a differential Q factor of respectively 40 and 55.…”

Section: "Above-ic" Rf-socmentioning

confidence: 99%

Process and Material Requirements for Successful Heterogonous Passive Component Integration in RF System

et al. 2006

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Applications using rf radios operating at frequencies above 1GHz are proliferating. The highest operating frequencies continue to increase and applications above 10GHz and up to 77GHz are already emerging. Systems become more complex and devices need to operate at several different frequency bands using different wireless standards. The rf-front end sections of these devices are characterized by a high diversity of components, in particular high precision passive components. In order to be produced cost-effectively, these elements need to be integrated along with the semiconductor devices. This paper describes the requirements for successful integration of rf-passive devices and proposes multilayer thin film technology as an effective rf-integration technology.

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High-$Q$ Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA

Cited by 29 publications

References 16 publications

Single Stage 38 GHz LNA using 0.1 μm GaAs HEMT

Single Stage 38 GHz LNA using 0.1 μm GaAs HEMT

Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices

Process and Material Requirements for Successful Heterogonous Passive Component Integration in RF System

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