2009
DOI: 10.1109/lmwc.2009.2027053
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High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $\mu$m CMOS Process

Abstract: In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 m CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and hi… Show more

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Cited by 48 publications
(24 citation statements)
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“…The transmission line used is a high-Q slow-wave coplanar transmission line [29]. The differential lines (CPW line) are on the top metal layer and the floating metal strips are on the lower metal layer.…”
Section: Experimental Results and Comparisonsmentioning
confidence: 99%
“…The transmission line used is a high-Q slow-wave coplanar transmission line [29]. The differential lines (CPW line) are on the top metal layer and the floating metal strips are on the lower metal layer.…”
Section: Experimental Results and Comparisonsmentioning
confidence: 99%
“…It is formed by a porous membrane filled with vertical metallic nanowires short-circuited to a ground plane, covered by a dielectric layer, on which the circuits are patterned, as shown in Figure l. Similarly to other slow-wave TLines [3][4][5], in the proposed IlTL the electric field is mainly concentrating in the dielectric material close to the microstrip in Fig. 1, while the magnetic field extends in the whole substrate.…”
Section: Principlementioning
confidence: 97%
“…Considerable effort has been invested in the past few years to develop high quality passive components in CMOS and BiCMOS technologies. As an example, high-performance slow-wave TLines, mostly CPW, have been successfully demonstrated in CMOS using the metallic interconnections of the BEOL, [3][4][5]. Despite the lower losses and the miniaturization provided by this type of TLine, the dimensions of the passive components remain significant, and since the In view of this problem, 3D integration techniques have been developed worldwide to combine multiple chips of different technologies on a common substrate, the "interposer".…”
Section: Introductionmentioning
confidence: 99%
“…The aim of this letter is to highlight the potential of patterned S-CPW to improve the measurement sensitivity compared to classical characterization methods. Since its first convincing results in CMOS technologies [3], the patterned shielded CPW topology has shown very high performance in various integrated technologies [4]- [6]. The principle of the proposed method is first explained.…”
Section: Introductionmentioning
confidence: 99%