This paper proposes differential design techniques for W-band CMOS applications. Transformers are used as passive matching circuits, which provide numerous advantages compared to traditional matching circuits. Stabilization and gain improvement of the differential pair is achieved by a wideband neutralization technique. These techniques are combined in a fully differential amplifier which is successfully measured. To our knowledge, this is the first fully differential 100 GHz CMOS amplifier.

In this paper, a fully integrated -band transmitter with on-chip dipole bondwire antenna implemented in 45 nm low-power CMOS is presented. The purpose of this 120 GHz wireless connector is to provide a high-speed short-range wireless communication link. On-chip frequency generation, insensitive to VCO pulling, is integrated together with a direct carrier quadrature vector modulator, ASK modulator, four-stage differential transformer-coupled power amplifier, and bondwire antenna. A -bit PRBS generator, capable of generating three parallel bit streams at a clock frequency of 8 GHz, is integrated on the same chip for measurement purposes. The transmitter is capable of efficiently generating BPSK, QPSK, and Star-QAM modulation formats. Data transmission over a distance up to 1 m is achieved for data rates as high as 2 Gb/s. For shorter distances, data rates up to 10 Gb/s are measured.Index Terms-CMOS, -band, 45 nm, millimeter-wave, on-chip antenna, RF front end, wireless connector.

A novel mm-wave phase modulating transmit architecture, capable of achieving data rates as high as 10 Gb/s is presented at 120 GHz. The circuit operates at a frequency of 120 GHz. The modulator consists of a differential branchline coupler and a high speed 4-to-1 analog multiplexer with direct digital input. Both a QPSK as well as a 8QAM constellation are supported. To achieve high output power, a 9-stage power amplifier is designed and connected to the multiplexer output. The complete chip is integrated in a 65 nm low power CMOS technology. Capacitive neutralization is used to achieve high gain and good stability for the MOS devices. Also, various differential transmission line topologies are investigated to achieve high performance in terms of loss and area consumption.

This paper presents a 120GHz fully integrated 65nm low power (LP) CMOS transmitter which achieves data rates above 10Gb/s. At these high frequencies an extremely high bandwidth is available. This allows multi gigabit per second communication which provides an answer to the ever increasing demand for higher data rates in wireless systems. However, wideband modulation of a 120GHz signal in 65nm LP CMOS is a challenge. To achieve a high data rate at these high frequencies, a straightforward and high speed phase modulator architecture is implemented. Figure 16.7.1 shows the complete schematic of the transmitter. The LO input signal is first buffered by a 2-stage buffer amplifier. The phase generation is done by a novel differential branch line coupler that generates two differential quadrature signals. These 2 signals are fed into two 6-stage driver amplifiers. By means of differential splitters, each signal is split in an in-phase and an inverted signal. This results in 4 differential signals with relative phases of 0, 90, 180 and 270 degrees, allowing phase modulation. The actual modulation is carried out by a 4-to-1 analog multiplexer which selects the generated 120GHz phases depending on the modulation scheme. The high-speed MUX is directly driven by digital signals and takes over the function of a conventional DAC and upconverter. The output of the MUX is buffered and fed into a 9-stage differential PA. The novel differential branchline coupler that generates the four phases, is based on a single ended branchline coupler. A 120GHz on chip signal has a wavelength of about 1.2mm. Conventional branchline couplers have a width and length of about /4, which is thus about 300µm. The use of slow-wave transmission lines, which have a higher artificial relative permittivity, resulting in lower phase velocity and shorter wavelengths, leads to a very compact design. The differential branchline coupler consumes an area of 140µm by 180µm which is almost 4 times less than a conventional branchline coupler. The 50 differential lines of the coupler are designed in the top metal layers and only have a bottom shield. A branchline coupler also needs a transmission line with a value of 50 / 2. To implement this 35 differential slow-wave line, an extra top shield is added. The use of a differential structure results in a less complicated and more compact slow-wave line than the single ended version. On top of that, the inverted signals are also available. The measured phases that are generated by this transmitter are shown in figure 16.7.3. The analog multiplexer consists of 4 differential pairs which can be switched on or off by their tail current source (See figure 16.7.2). The tail current source is directly driven by a buffered differential digital signal. If two quadrature phase channels are switched on together, an additional 45° interpolated phase can be realized, resulting in an 8-point QAM constellation. The AM of this signal can be removed by pushing the PA into saturation, which also improves the overall power efficiency ...

Abstract-Existing radio frequency (RF) integrated circuit (IC) design automation methods focus on the synthesis of circuits at a few GHz, typically less than 10 GHz. That framework is difficult to apply to RF IC synthesis at mm-wave frequencies (e.g., 60-100 GHz). In this paper, a new method, called efficient machine learning-based differential evolution, is presented for mm-wave frequency linear RF amplifier synthesis. By using electromagnetic (EM) simulations to evaluate the key passive components, the evaluation of circuit performances is accurate and solves the limitations of parasitic-included equivalent circuit models and predefined layout templates used in the existing synthesis framework. A decomposition method separates the design variables that require expensive EM simulations and the variables that only need cheap circuit simulations. Hence, a lowdimensional expensive optimization problem is generated. By the newly proposed core algorithm integrating adaptive population generation, naive Bayes classification, Gaussian process and differential evolution, the generated low-dimensional expensive optimization problem can be solved efficiently (by the online surrogate model), and global search (by evolutionary computation) can be achieved. A 100 GHz three-stage differential amplifier is synthesized in a 90 nm CMOS technology. The power gain reaches 10 dB with more than 20 GHz bandwidth. The synthesis costs only 25 h, having a comparable result and a nine times speed enhancement compared with directly using the EM simulator and global optimization algorithms.