High-Quality Statistical Test Compression With Narrow ATE Interface

Tenentes, Vasileios; Kavousianos, X.

doi:10.1109/tcad.2013.2256394

Cited by 11 publications

(2 citation statements)

References 44 publications

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“…Non-LFSR-based test data compression approaches were developed for the case where a given test set needs to be compressed and detailed information about the circuit is not available [Jas et al 2003;Hashempour and Lombardi 2005;Larsson et al 2007;Li et al 2003;Lingappan et al 2006;Nourani and Tehranipour 2005;Ruan and Katti 2007;Tenentes and Kavousianos 2013;Touba 2006;Wolff et al 2004;Xiang et al 2012;Zhou and Balakrishnan 2007]. Such information is needed for computing test cubes or otherwise modifying the test set.…”

Section: Non-lfsr-based Approachesmentioning

confidence: 99%

Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests

Pomeranz

2016

ACM Trans. Des. Autom. Electron. Syst.

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This article describes a procedure for test data compression targeting functional and partially functional broadside tests. The scan-in state of such a test is either a reachable state or has a known Hamming distance from a reachable state. Reachable states are fully specified, while the popular LFSR-based test data compression methods require the use of incompletely specified test cubes. The test data compression approach considered in this article is based on the use of periodic scan-in states. Such states require the storage of a period that can be significantly shorter than a scan-in state, thus providing test data compression. The procedure computes a set of periods that is sufficient for detecting all the detectable target faults. Considering the scan-in states that the periods produce, the procedure ranks the periods based on the distances of the scan-in states from reachable states, and the lengths of the periods. Functional and partially functional broadside tests are generated preferring shorter periods with smaller Hamming distances. The results are compared with those of an LFSR-based approach.

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Section: Non-lfsr-based Approachesmentioning

confidence: 99%

Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests

Pomeranz

2016

ACM Trans. Des. Autom. Electron. Syst.

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“…In [24], a test set enrichment technique for the selection of test patterns is proposed. Output deviations have also been used for enriching the unmodeled defect coverage of tests during x-filling [5] and linear [11,12,21] and statistical [22] compression. The output deviation-based metric proposed in [12], was shown to increase the unmodeled defect coverage of test vectors by considering both timing-independent defects, such as stuckat faults, and timing-dependent defects, such as transition faults which require two patterns.…”

Section: Introductionmentioning

confidence: 99%

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

et al. 2017

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Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%.

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