High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link

Abstract

A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughput in 65nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a lowcrosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel relaxation circuit and a differential channel receiver.

A low latency wormhole router for asynchronous on-chip networks

“…A simple solution for the long interconnect between routers is to insert more pipeline stages in it. Many papers have concentrated on this long wire effect [16,17,18] and, thus, it is beyond the scope of this paper. The loop traversing the crossbar is the critical cycle.…”

Asynchronous Current Mode Serial Communication

“…LEDR encoding is performed on the fly at the very low cost of a XOR and a few transmission gates [14]. LEDR is a systematic code (namely, the original data are included unchanged in the code) and therefore requires no decoder logic at the receiver side, saving power and latency.…”

“…[15] Bit-serial communication links offer an alternative to bit-parallel interconnects, mitigating the issues of area, routability and power, since there are fewer wires, fewer line drivers, and fewer repeaters. To support a throughput similar to bit-parallel links, several asynchronous wide-bandwidth serial link circuits [11], [14]- [21], all operating faster than the system clock, have been proposed. Several of the wide-bandwidth serial links are listed in Table I according to their minimal data cycle.…”

“…High-speed serial links, having data cycle of a few gate delays (down to single gate-delay cycle), have been recently proposed [14]- [22]. These fast links employ wave-pipelining [23]- [25], low-swing differential signaling, fast clock generators and asynchronous protocols.…”

“…1). Previously [14], [15], we investigated a highspeed [0]serial link with voltage sensing at the receiver side. The link employed novel high-speed serializer and de-serializer wave-pipelining circuits.…”