High-speed 2-D hardware convolution architecture based on VLSI systolic arrays

Haule, D.D.; Malowany, A.S.

doi:10.1109/pacrim.1989.48304

Cited by 4 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…With the selected systolic architecture, we can decompose the 2-D convolution into several small and fast 1-D convolution cells [10]. The use of several systolic cells in a processor allows concurrent multiplications and additions.…”

Section: Hardware Implementationmentioning

confidence: 99%

A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks

Zhang

Bermak

Boussaid

et al. 2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

View full text Add to dashboard Cite

In this paper, we present a compact, low cost, real-time CMOS hardware architecture for face detection. The proposed architecture is based on a VLSI-friendly implementation of Shunting Inhibitory Convolutional Neural Networks (SICoNN). Reported experimental results show that the proposed architecture can detect faces with 93% detection accuracy at 5% false alarm rate. A VLSI Systolic architecture was considered to further optimize the design in terms of execution speed, power dissipation and area. Potential applications of the proposed face detection hardware include consumer electronics, security, monitoring and head-counting. Disciplines Physical Sciences and Mathematics

show abstract

Section: Hardware Implementationmentioning

confidence: 99%

A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks

Zhang

Bermak

Boussaid

et al. 2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

View full text Add to dashboard Cite

show abstract

“…Much effort has been directed towards speeding up the convolution process through hardware implementation [3][4][5][6][7][8][9]. This is because convolution is a computation intensive algorithm as shown in Equation 1 and illustrated in Figure 1.1.…”

Section: Introductionmentioning

confidence: 99%

New scalable systolic array processor architecture for simultaneous discrete convolution of k different (n × n) filter coefficient planes with a single image plane

2003

View full text Add to dashboard Cite

A new high-performance scalable systolic array processor architecture module is presented which can simultaneously convolute k different (n x n) Filter Coefficient (FC) planes with a single (i x j) pixel Input Image Plane (IP). The architecture will have the capability to simultaneously perform convolution of k different (n × n) FC planes on 600dpi (dot per inch) IPs of size 8½"×11" at a rate such that k convoluted Output Image (OI) plane pixels are output each system clock cycle for a system clock cycle time of less than 10 nanoseconds. Bit-parallel arithmetic is used and each IP pixel is 8-bits in length and each FC plane coefficient is 6-bits in length. A new pipelined systolic type architecture module is first developed which can generate one convoluted OI plane pixel per system clock cycle using a level of "r" hardware resources for the case of (n = 5). The architecture is then extended in a scalable and deeper pipelined manner to allow simultaneous convolution of a single IP pixel, with k different (n x n) FC planes for the case of (n = 5), within one system clock cycle, utilizing less than (k x r) hardware resources. Synthesis and post-implementation VHDL simulation results are shown for an experimental model of the architecture which validates the scalability and functionality of the architecture. Simulation results demonstrate the performance of the architecture to be directly proportional to pipeline depth.

show abstract