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Many studies for the preliminary definition of a space teleoperated robotic devices are recently completed or under development. One example of such devices is the Flight Telerobotic Servicer (FTS) developed by NASA. These studies will assist astronauts in many ot the on- and off-board tasks of assembly, maintenance, servicing and inspection of the Space Station. This paper makes an assessment of the role that teleprogramming may have in furthering the automation capabilities of these devices by extending their capacity for growth and evolution. Relevant system engineering design issues are identified for its programming. An outline of teleprogramming environments is given which comprises of task planning and interpretation, simulation, specialized modules known as system agents and world model manager (influencing teleoperator decisions at a remote worksite). A Space Robotic Workcell (SRW) is a collection of robots, sensors, and other equipment grouped in a cooperative environment to perform various complex tasks in space. Due to their distributed nature, the control and programming of SRWs is often a difficult task, for which dedicated space environments have to be designed. There is clearly established need to perform intervention tasks remotely in hazardous environments by machines. Examples of this need that are highly relevant to our discussion are space safety applications, space exploration and underwater structure maintenance and repair. In this paper we focus on Space Robotics & Automation. We have discussed a detailed study of autonomy versus teleoperation for intervention robots making a case for task level teleprogramming as a new emerging field in Telerobotics. A rationale for teleprogramming and its techniques, Expert Systems, SRW Subsystem Agents, SRW Task Planner and SRW Plan (for growth and evolution) are also covered in this paper.

This paper summarizes the design of a convolution processor card that is very low in cost, easy to use and most importantly, performs a 9x9 convolution in less than a second. Its high -performance is attributed to a VLSI systolic convolution cell which has been designed in our laboratories and to an efficient supporting data path architecture. The new Intel 82258 Advanced DMA Controller is used to perform each pixel transfer to and from the host computer's memory. Due to the DMA's software programmability, pictures of any size can be processed. The circuit is assembled on a 36 column MULTIBUS bus card and is installed on an Intel System 310 running iRMX 286 real -time multitasking operating system. CONVOLUTION COMPLEXITYIn our laboratory, images are obtained using a black and white camera and a frame grabber that digitalizes each pixel into 256 gray scale levels. Starting from the top of the image, rows are stored one after the other. Adjacent pixels in a row occupy consecutive bytes in memory. The present image resolution used is 512x512 ABSTRACT This paper summarizes the design of a convolution processor card that is very low in cost, easy to use and most importantly, performs a 9x9 convolution in less than a second. Its high-performance is attributed to a VLSI systolic convolution cell which has been designed in our laboratories and to an efficient supporting data path architecture. The new Intel 82258 Advanced DMA Controller is used to perform each pixel transfer to and from the host computer's memory. Due to the DMA's software programmability, pictures of any size can be processed. The circuit is assembled on a 36 column MULTIBUS bus card and is installed on an Intel System 310 running iRMX 286 real-time multitasking operating system. SPIEVol. 1001 Visual Communications and Image Processing'88 / 469Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx