High-Speed 64-Bit Binary Comparator using Two Different Logic Styles

Anjuli, Anjuli; Anand, Satyajit

doi:10.5120/11463-7071

Cited by 4 publications

(4 citation statements)

References 7 publications

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“…Different 2 bit Comparator designs by using different logic styles and their comparison have been presented in [5]. A CMOS and TG 2 bit comparator design provides full voltage swing between 0 and V DD .…”

Section: Fig 3: 2-bit Comparator Using Cmos Logic Style [5]mentioning

confidence: 99%

Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic

Sharma¹,

Singh²,

Kajla³

2013

IJCA

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In this paper an area efficient 17T 1-bit hybrid comparator design has been presented by hybridizing PTL and GDI techniques. The proposed 1-bit comparator design consist of 9 NMOS and 8 PMOS. A PTL and GDI full adder module has been used which consume less area at 120 nm as compared with the previous full adder designs. The proposed Hybrid 1-bit comparator design is based on this area efficient 9T full adder module. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the used full adder module. Full adder modules outputs have been used for the generation of three different output of 1-bit comparator designs. The proposed 1-bit comparator has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. Also the simulation of layout and parametric analysis has been done for the proposed 1-bit comparator design. Power and current variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed hybrid adder is 329.3µm 2 on 120nm technology. At 1.4V input supply voltage the proposed 1-bit hybrid comparator consume 0.367mW power at BSIM-4 and 0.411mW power at LEVEL-3 and 2.313mA current at BSIM-4 and 3.047mA current at LEVEL-3 model

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Section: Fig 3: 2-bit Comparator Using Cmos Logic Style [5]mentioning

confidence: 99%

Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic

Sharma¹,

Singh²,

Kajla³

2013

IJCA

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“…In this paper, a comparative analysis about the Area and Power of different logic design of comparator has been presented. Furthermore, based on the comparator proposed in [13], a comparator is presented which consumes so much area and power on the other hand area can be reduced by making these circuit by semi custom technique. This modification results in considerably area efficient and power efficient when compared with the other one.…”

Section: Introductionmentioning

confidence: 99%

Area Efficient Layout Design of CMOS Comparator using PTL Logic

Jyoti¹,

Mehra²

2015

IJCA

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Comparator is a very useful combinational logic circuit. In this paper performance analysis of CMOS Comparator and PTL logic design has been shown. In the design of integrated circuits, several logic families is being used which is described by Pass Transistor Logic (PTL). It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. The layout of 2-bit comparator is developed using automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is optimized manually. The result shows that semicustom layout of PTL logic consumes 35% less area as compared to CMOS logic design to provide area efficient solution.

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“…The improved system is realized as [2] using tanner EDA simulation tool V7.0 1.25µm technology model file ml2_125.md with minimum supply voltage of 2.5V.…”

Section: Model Usedmentioning

confidence: 99%