High speed differential voltage clampedcurrent mode ring oscillator

Jeong, Dongin; Chae, Seung‐Hoon; Song, Wonchul; Cho, G.H.

doi:10.1049/el:19970798

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Cited by 5 publications

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“…Still, an ECL-like current-mode differential pair, as shown in Fig. 11, is used as a delay cell [17], [18] to achieve high common-mode rejection in a four-stage ring oscillator. The coarse tuning of the ring-oscillator's center frequency is achieved by the bias Vbpo1 (or through the use of a digital-to-analog converter), and a fine tuning technique is needed for the PLL voltage-control path.…”

Section: Vcomentioning

confidence: 99%

Fast Switching Frequency Synthesizer with a DiscriminatorAided Phase Detector

2009

Phase-Locking in High-Performance Systems

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A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-m CMOS process, and the output phase noise is 99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW.

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Section: Vcomentioning

confidence: 99%