High‐speed energy‐efficient bi‐directional transceiver for on‐chip global interconnects

Wary, Nijwm; Mandal, Pradip

doi:10.1049/iet-cds.2014.0351

Cited by 9 publications

(4 citation statements)

References 23 publications

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“…Codes that correct errors are essential to modern civilization and are used in devices from modems to planetary satellites [15][16][17][18][19][20][21]. The theory is mature, difficult, and mathematically oriented, with tens of thousands of scholarly papers and books, but this project will describe only a simple and elegant code, discovered in 1949.…”

Section: ░ 2 Background Of Hamming Codementioning

confidence: 99%

Design and Implementation of Triplication Error Correction Using Hamming Code

Priyadharshini, L,

Krishnan, P.,

, K.

2023

IIJSR

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Section: ░ 2 Background Of Hamming Codementioning

confidence: 99%

Design and Implementation of Triplication Error Correction Using Hamming Code

Priyadharshini, L,

Krishnan, P.,

, K.

2023

IIJSR

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“…[7][8][9][10][11][12][13][14][15][16] Besides, some half-duplex signaling solutions have been presented in the literature. [17][18][19][20] However, the overall bandwidth of the system reduces to half because of the timesharing between the receiving and the transmitting cycles. The simultaneous bidirectional signaling solution can be used to overcome the time-sharing problem.…”

Section: Introductionmentioning

confidence: 99%

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

Jarihani

Sturm

Tonello

2021

Circuit Theory & Apps

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This paper presents a high‐speed simultaneous bidirectional transceiver (SBT) for on‐chip wireline communications. A MOS hybrid transistor is utilized to split the received data from the superimposed signal at both ends of the on‐chip interconnection with the assistance of two drivers, namely main and auxiliary. Moreover, a high‐pass filter (HPF) is used as a differentiator to generate the echo cancelation signal. Consequently, the echo‐cancelation for simultaneous bidirectional signaling (SBS) is realized by the combination of the hybrid device and the differentiator. The proposed SBT has been designed and evaluated using 28‐nm CMOS technology over a narrow 5‐mm on‐chip interconnection, which possesses 11.9‐dB loss at the Nyquist frequency (half a bit rate). The energy‐efficiency of the proposed full‐duplex transceiver (FDT) for 20‐Gbps simultaneous bidirectional data transmission is 0.147 PJ/b/mm. The performance results show that the proposed SBT has better overall performance compared to the previous architectures reported in the literature to date. The layout of the presented SBT occupies a low area of 1574 μm2.

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“…In addition to the aforementioned techniques, half-duplex signaling schemes are reported in [18][19][20][21]. This type of signaling allows us to use the same interconnect for both transmitting and receiving the data.…”

Section: Introductionmentioning

confidence: 99%

A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

et al. 2020

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A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency.

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High‐speed energy‐efficient bi‐directional transceiver for on‐chip global interconnects

Cited by 9 publications

References 23 publications

Design and Implementation of Triplication Error Correction Using Hamming Code

Design and Implementation of Triplication Error Correction Using Hamming Code

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

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