High speed error correction in continuous-time ramp generators using loop gain optimization

Asish, L.; Prasobh, Sankar R S; Krishnan, Aravind; Bhuvan, B.

doi:10.1109/tencon.2019.8929480

Cited by 3 publications

(1 citation statement)

References 2 publications

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“…The differential continuous-time ramp generator described incorporates error correction capability, potentially introducing complexity and increasing fabrication costs due to its intricate circuitry. The implementation of error correction circuits with negative feedback adds further complexity, making the circuit design challenging to troubleshoot and maintain while potentially raising manufacturing costs [2]. The on-chip ramp generator employs a fully-differential switched-capacitor integrator and operates within a servo-loop con guration, necessitating feedback control for performance optimization.…”

Section: Introductionmentioning

confidence: 99%

High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology

Malathi,

Malavika

2024

Preprint

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Analog-to-digital converters (ADCs) are essential components in contemporary electronic systems for translating continuous analog signals into digital formats. Emphasizing low power consumption and high conversion efficiency, the project addresses the escalating demand for high-resolution electronic devices. The primary objective is to achieve optimal resolution, crucial for environmental monitoring which demands precision. ADC architecture Ramp ADC is the focal point of the design, implemented within an 18nm FinFET technology framework. The Ramp ADC, with its comparator array and ramp generator, offers simplicity and potential for high-speed applications. The primary objective of this project is to employ a range of design techniques and modifications aimed at reducing power consumption in ADC architecture, all while minimizing the impact on crucial performance metrics, including resolution, speed, and complexity. The comparative analysis focuses on the average power of the ADC, each possessing a resolution of 13 bits. Specifically, modifications applied to the Ramp ADC yield an impressive 47% reduction in average dynamic power, coupled with a notable 28% reduction in static power compared with the existing.

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Section: Introductionmentioning

confidence: 99%

High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology

Malathi,

Malavika

2024

Preprint

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Design of Stable Error-Correction Ramp Generators Considering Process and Run-Time Variations

Sankar

Asish

Bhuvan

2019

2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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An Opamp-Less PVT Compensation Structure for Ramp Generator Circuit

Padash

Yargholi

Baghini

2020

J CIRCUIT SYST COMP

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Accurate ramp signal, with low power dissipation, is highly demanded, for applications like counter ADC. This paper presents a novel low power ramp generator circuit with a negative feedback loop for compensation of the variations in process, voltage, and temperature (PVT). While using an opamp for PVT compensation has been essential in the previous ramp generator structures, the proposed ramp generator is opamp-less. Derived equations of the proposed ramp generator circuit show that PVT compensation structure works effectively. In addition, the circuit design and simulations were done in TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology. Corner analysis shows that integral non-linearity (INL) of the ramp signal is about 3.7[Formula: see text]mV, for a wide temperature range, while the power dissipation of the circuit is about 1.16[Formula: see text][Formula: see text]W.

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High speed error correction in continuous-time ramp generators using loop gain optimization

Cited by 3 publications

References 2 publications

High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology

High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology

Design of Stable Error-Correction Ramp Generators Considering Process and Run-Time Variations

An Opamp-Less PVT Compensation Structure for Ramp Generator Circuit

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