High Speed FPGA-Based Implementations of Delayed-LMS Filters

IEICE Electron. Express

Wang

et al. 2017

Motivated by improvement of convergence characteristics and throughput, this work develops a delay-optimized VLSI realization of the adaptive filter based on the 2-parallel delayed LMS (PDLMS) algorithm. The proposed design uses a novel parallel FIR filter structure based on the fast FIR algorithm. The throughput of the proposed architecture is not only two times that of the traditional structure at the same frequency, but also the convergence characteristic is close to that of the LMS algorithm. The finegrained dot-product unit, fine-grained fused multiply-add unit and multipleinput-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed architecture of an 8-tap filter has nearly 25% less power and nearly 24% less area-delay-product (ADP) than the best existing structure.

Section: Results and Comparisonsmentioning

confidence: 90%

Section: Results and Comparisonsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Delay-optimized realization of 2-parallel delayed LMS adaptive FIR filter

IEICE Electron. Express

Wang

et al. 2017

“…Some researchers have done a lot of work on the systolic architectures of the DLMS algorithm in [6,7,8]. Since the number of registers of systolic architectures is more than that of conventional architecture in [9], a more power consumption and larger area will be generated.…”

Section: Introductionmentioning

confidence: 99%

VLSI implementation of the modified sign-error LMS adaptive algorithm

Wang

IEICE Electron. Express

et al. 2017

Motivated by reduction of computational complexity, this work develops a delay-optimized VLSI architecture of the adaptive filter based on the modified sign-error LMS (MSLMS) algorithm. The proposed algorithm uses a three-level quantization strategy applied to the modified sign function containing a threshold parameter. The amount of computation of the proposed architecture is not only less than half of the traditional structure, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed design for filter length 8-tap has roughly 31% less power and 53% less area-delay-product (ADP) than the best of existing structures.

FPGA‐Based Implementation of Signal Processing Systems

Final Statements

2008

Designations used by companies to distinguish their products are often claimed as trademarks. All brand names and product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective owners. The publisher is not associated with any product or vendor mentioned in this book. This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold on the understanding that the publisher is not engaged in rendering professional services. If professional advice or other expert assistance is required, the services of a competent professional should be sought. Library of Congress Cataloging-in-Publication DataWood, Roger.FPGA-based implementation of complex signal processing systems / Roger Wood ... [et al.]. p. cm. Includes bibliographical references and index.