High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective

2014 IEEE International Conference on Evolvable Systems

Bale

et al. 2014

Circuit performance optimisation such as increasing speed and minimizing power consumption is the most important design goal for circuit designers next to correct functionality. This is generally also a very complex problem where, in order to solve it, several factors such as device characteristics, circuit topology, and circuit functionality must be considered. Particularly, as technology has scaled to the atomistic level, the resulting uncertainty factors further affect circuit performance. In this paper, we propose combining a modified genetic algorithm with dynamic gene mutation and device layout motif selection for circuit performance improvement. We explore novel device layout motifs (O shape device) to exploit effects of device layout at the atomistic level in order to improve characteristics of circuits and combine them with a modified GA for automatic circuit optimisation. Additionally, in order to overcome local optima and premature convergence, a dynamic gene mutation rate is performed within the GA. The experimental results show that this methodology can achieve more than 30% delay reduction through mixed combinations of O shape devices and regular devices in a circuit, compared to circuits built of only regular devices. At the same time, the local optima are also reliably avoided due to the dynamic gene mutation.

Section: Introductionmentioning

confidence: 99%

Circuit design optimisation using a modified genetic algorithm and device layout motifs

Xiao

2014 IEEE International Conference on Evolvable Systems

Bale

et al. 2014

“…An alternative approach is to use topologies optimised specifically to be variability tolerant within Standard Cell Libraries (SCLs). One potential methodology for achieving this is to use Evolutionary Algorithms (EAs), which have been used in the past to optimise existing CMOS designs for a number of criteria, such as delay [36], area [32], power and yield [42]. EAs have also been used to produce new and unconventional design topologies at both the gate level [27] and device level [40], and also fault-tolerant designs [13,14].…”

Section: Introductionmentioning

confidence: 99%

The evolution of standard cell libraries for future technology nodes

Genet Program Evolvable Mach

Hilder

Reid

et al. 2011

Evolvable Hardware has been a discipline for over 15 years. Its application has ranged from simple circuit design to antenna design. However, research in the field has often been criticised for not addressing real world problems. Intrinsic variability has been recognised as one of the major challenges facing the semiconductor industry. This paper describes an approach that optimises designs within a standard cell library by altering the transistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm to optimise the device widths within a standard cell. The designs are analysed using statistically enhanced transistor models (based on 3D-atomistic simulations) and statistical SPICE simulations. The goal is to extract high-speed and low-power designs, which are more tolerant to the random fluctuations present in current and future technology nodes. The results

“…An alternative approach is to use circuit topologies optimized to be variability tolerant within standard cell libraries (SCLs). In the past, evolutionary algorithms (EAs) have been used to optimize existing CMOS circuit designs for a number of criteria, such as delay (Salomon & Sill 2007), area (Noren & Ross 2001), power and yield (Takahashi et al 2005). EAs have also been used to produce new unconventional designs at both the gate level (Miller et al 2000) and device level (Streeter et al 2003), as well as fault-tolerant designs (Djupdal & Haddow 2007).…”

Section: Introductionmentioning

confidence: 99%

Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid

Phil. Trans. R. Soc. A.

Sinnott

Stewart

et al. 2010

The project Meeting the Design Challenges of nano-CMOS Electronics (http://www. nanocmos.ac.uk) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function exploiting the nano-CMOS grid. The results show that the impact of threshold voltage variation can be reduced by optimizing transistor widths, and indicate that a similar method could be extended to the optimization of larger circuits.