High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Abstract

A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive-and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-µm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz-3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 µW/MHz. Index Terms-Clock generator, delay-locked loop (DLL), edge combiner, frequency multiplier.

A DLL based clock multiplier using rotational DCDL and PRNG for spur reduction

“…The DLL-based clock multiplication uses an edge-combining technique [6] from multiple clock edges at the delay chain. Therefore, any mismatches in delay cell due to process variation and inadequate layout design cause spurious tone at output [7,8].…”

Design of Delay Locked Loop with Frequency Division Technique

“…In the recent years, the delay locked loop (DLL)is used for synchronization, clock generation [1], clock deskewing, and data recovery [2]. Compared with phase locked loop (PLL) [3], DLL has better jitter performance because of no jitter accumulation at the end of the voltage-controlled delay line.…”

Reduction of Power Supply Induced Jitter with Applications to DDR Controllers

“…Higher data rate applications require higher performance clock synthesizers [32]. Delay locked loop (DLL) based frequency multipliers have been widely used in interchip communication interfaces [13] [33], clock distribution networks [34] [35] and radio frequency system applications [36] [37]. These functions can also be achieved by PLLs, but…”

“…In particular, the jitter accumulation phenomenon makes PLLs more susceptible to power-supply and substrate noise [38], [39]. Compared with PLLs DLLs have the advantages of ease of design, better immunity to on-chip noise, and more stability [34] [40].…”

“…Comparison of PLL and MDLL is summarized in Table 2.1. [39] first-order system [43] unconditionally stable [13] easy to design [85] easy to integrate LF [34] reference…”