High speed merged-datapath design for run-time reconfigurable systems

Abstract

Datapath merging is an efficient high level synthesis method to merge Data Flow Graphs (DFGs), corresponding to two or more computational intensive loops. This process creates a general purpose datapaths (merged datapaths) instead of multiple datapaths that results in shorter bit-stream length and therefore reduces the configuration time in reconfigurable systems. The merged datapath, however has worse loop execution time. This paper represents two datapath merging algorithms to address this problem. These algorithms consider the impact of adding multiplexer's latency to the critical path delay of the merged datapath. The former algorithm merges DFGs from the biggest DFG to the smallest one to make high speed merged datapath. The latter merges DFGs in steps, and in the final step, it combines the resources inside the merged datapath to achieve additional reduction in configuration time. The proposed techniques are evaluated using several Mediabench applications. The experimental results show a significant reduction, up to 35% in loops execution time for the first algorithm and up to 27% reduction for the second algorithm in comparison to previous datapath merging algorithm.

Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

“…The second one is a datapath merging technique in [8] that searches inter-DFG resource sharing for datapath configuration time reduction in RTR systems. The third technique is the datapath merging technique in [10] for the overhead reduction in RTR systems that aims at high-speed merged datapaths.…”

“…The second technique in [8] uses the Maximum weighted clique approach to merge DFGs and is referred to as Max-Clique. The third technique in [10] which uses Bounded execution time Clique to make high speed merged datapath is referred as Bounded-Clique. Our approach, which is based on computing the MAT-Clique is referred to as MAT-Clique.…”

“…Thus, by significant amount of kernel iterations, this may influence the overall execution time of a module. This disadvantage was considered in [10] where a method to create high-speed merged datapaths is proposed. This technique, however, cannot efficiently reduce T A in RTR systems.…”

“…To quantify the efficiency of merged datapaths the Module Aggregate Time (T A ) that consists of both, the configuration time and the execution time of the corresponding kernels is used. A trade-off exists between the merged datapath configuration time and the execution time of the kernels [10].…”

A new multi-objective mathematical model for the high-level synthesis of integrated circuits

“…The heuristic algorithms proposed by Cong et al (2010) and Casseau and Gal (2009) try to achieve scheduling under latency constraints while assigning functional units and multiplexers at the same time. In the study of Fazlali et al (2009), scheduling and assignment are performed iteratively so as to avoid multiplexers on the critical path. In a recent method proposed by Hadjis et al (2012) efficient patterns are extracted by using the assignment.…”