High-Speed Pipeline Implementation Of Radix-2 Dif Algorithm

The precise analysis and accurate measurement of harmonic provides a reliable scientific industrial application. However, the high performance DSP processor is the important method of electrical harmonic analysis. Hence, in this research work, the effort was taken to design a novel high-resolution single 1024-point fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) processors for improvement of the harmonic measurement techniques. Meanwhile the project is started with design and simulation to demonstrate the benefit that is achieved by the proposed 1024-point FFT/IFFT processor. Pipelined structure is incorporated in order to enhance the system efficiency. As such, a pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints. The proposed FFT makes use of programmable fixed-point/floating-point to realize higher precision FFT.

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Design of 16-point Radix-4 Fast Fourier Transform in 0.18Âµm CMOS Technology

Palaniappan¹,

Zulkifli²

2007

American J. of Applied Sciences

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This paper introduces detail design of semi-custom CMOS Fast Fourier Transform (FFT) architecture for computing 16-point radix-4 FFT. FFT is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication application as an important block for various multi-carrier systems such as for WLAN (Wireless local area network). This paper describes the design of an ASIC (Application Specific Integrated Circuit) CMOS FFT processor for 16-point radix-4 complex FFT computation, realized utilizing 0.18µm standard CMOS technology. Fixed point data format is preferred in comparison of floating point data format for a shorter dynamic range and reduced hardware utilization; thus, catering to the needs of portability. Furthermore, computations results at particular stage are rounded to avoid overflow issue and to be stored in register. The computation speed of the design is observed to be 50MHz after the synthesis process. Compared to traditional radix-4 algorithm the architecture proposed for 16-point FFT results in 1.73% of power saving and 5.5% of area reduction.

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High-Speed Pipeline Implementation Of Radix-2 Dif Algorithm

Cited by 3 publications

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Multiple-Valued Logic Networks with Regular Structure Obtained from Fast Fourier Transforms on Finite Groups

Multiple-Valued Logic Networks with Regular Structure Obtained from Fast Fourier Transforms on Finite Groups

Characteristic analysis of 1024-point quantized Radix-2 FFT/IFFT processor

Design of 16-point Radix-4 Fast Fourier Transform in 0.18Âµm CMOS Technology

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