In this manuscript, recent progress in the area of resistive random access memory (RRAM) technology which is considered one of the most standout emerging memory technologies owing to its high speed, low cost, enhanced storage density, potential applications in various fields, and excellent scalability is comprehensively reviewed. First, a brief overview of the field of emerging memory technologies is provided. The material properties, resistance switching mechanism, and electrical characteristics of RRAM are discussed. Also, various issues such as endurance, retention, uniformity, and the effect of operating temperature and random telegraph noise (RTN) are elaborated. A discussion on multilevel cell (MLC) storage capability of RRAM, which is attractive for achieving increased storage density and low cost is presented. Different operation schemes to achieve reliable MLC operation along with their physical mechanisms have been provided. In addition, an elaborate description of switching methodologies and current voltage relationships for various popular RRAM models is covered in this work. The prospective applications of RRAM to various fields such as security, neuromorphic computing, and non-volatile logic systems are addressed briefly. The present review article concludes with the discussion on the challenges and future prospects of the RRAM.

Porous metal structures have emerged as a promising solution in repairing and replacing damaged bone in biomedical applications. With the advent of additive manufacturing technology, fabrication of porous scaffold architecture of different unit cell types with desired parameters can replicate the biomechanical properties of the natural bone, thereby overcoming the issues, such as stress shielding effect, to avoid implant failure. The purpose of this research was to investigate the influence of cube and gyroid unit cell types, with pore size ranging from 300 to 600 µm, on porosity and mechanical behavior of titanium alloy (Ti6Al4V) scaffolds. Scaffold samples were modeled and analyzed using finite element analysis (FEA) following the ISO standard (ISO 13314). Selective laser melting (SLM) process was used to manufacture five samples of each type. Morphological characterization of samples was performed through micro CT Scan system and the samples were later subjected to compression testing to assess the mechanical behavior of scaffolds. Numerical and experimental analysis of samples show porosity greater than 50% for all types, which is in agreement with desired porosity range of natural bone. Mechanical properties of samples depict that values of elastic modulus and yield strength decreases with increase in porosity, with elastic modulus reduced up to 3 GPa and yield strength decreased to 7 MPa. However, while comparing with natural bone properties, only cube and gyroid structure with pore size 300 µm falls under the category of giving similar properties to that of natural bone. Analysis of porous scaffolds show promising results for application in orthopedic implants. Application of optimum scaffold structures to implants can reduce the premature failure of implants and increase the reliability of prosthetics.

In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50% in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11% reduction in transistor count is observed while for TM design, around 38% reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations. INDEX TERMS Multiple valued logic (MVL), ternary logic systems, emerging technologies, carbon nanotube field effect transistor (CNTFET), resistive random access memory (RRAM).

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