2012 IEEE Energy Conversion Congress and Exposition (ECCE) 2012
DOI: 10.1109/ecce.2012.6342520
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High-speed resonant gate driver with controlled peak gate voltage for silicon carbide MOSFETs

Abstract: Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimenta… Show more

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Cited by 25 publications
(11 citation statements)
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“…All of these papers indicate that the primary method available to designers for managing the natural ring-down phenomenon is the reduction of switching speed. Indeed, two additional papers go so far as to claim that the aggregate inductance of the gate loop establishes a practical limit to the switching frequency achievable in hard-switched applications [22], [23]. This is an important observation, as it reinforces the claim that high switching speed brings with it increased risk to the occurrence of various switching anomalies, of which self-sustained oscillation is an example.…”
Section: Literature Reviewmentioning
confidence: 80%
“…All of these papers indicate that the primary method available to designers for managing the natural ring-down phenomenon is the reduction of switching speed. Indeed, two additional papers go so far as to claim that the aggregate inductance of the gate loop establishes a practical limit to the switching frequency achievable in hard-switched applications [22], [23]. This is an important observation, as it reinforces the claim that high switching speed brings with it increased risk to the occurrence of various switching anomalies, of which self-sustained oscillation is an example.…”
Section: Literature Reviewmentioning
confidence: 80%
“…Several novel methods have been investigated to move a portion of the gate driver circuitry closer to the power devices [74], [75]. The most broadly applicable methods, however, will move the gate driver directly inside the package with the power device, as shown in Fig.…”
Section: Integrated Circuitsmentioning
confidence: 99%
“…The negative low-state gate voltage (-5V) is used to provide the margin of preventing the potential shoot-through failure caused by the induced spurious gate voltage. The high-state gate voltage should be as high as possible while within the maximum rated gate voltage, to minimize the conduction losses of SiC MOSFETs [17], and +20V is selected.…”
Section: Designed Split Output Converter and Measurement Equipmentmentioning
confidence: 99%