High speed S-box architecture for Advanced Encryption Standard

Rachh, Rashmi; AnandaMohan, P. V.; Anami, Basavaraj S.

doi:10.1109/imsaa.2011.6156342

Cited by 6 publications

(3 citation statements)

References 16 publications

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“…By contrast, the studies, [14] and [15], proposed a 4-stage pipelined S-box. The work [16] adopted the pre-computation technique with three block design of S-box. In [17], modified MUX based Sbox was introduced in AES to reduce the area without affecting the throughput.…”

Section: Introductionmentioning

confidence: 99%

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

et al. 2022

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This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF((2 2 ) 2 ), is reduced. The squaring and multiplication with constant λ in GF((2 2 ) 2 ) are combined and optimized as well. Moreover, the multiplicative inversion in GF((2 2 ) 2 ) is manually optimized. Furthermore, the S-box and inverse Sbox are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.INDEX TERMS Advanced encryption standard (AES), Composite field arithmetic (CFA), S-box, VLSI architecture.

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Section: Introductionmentioning

confidence: 99%

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

et al. 2022

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“…Since the beginning of study of the Advanced Encryption Standard, it has been thoroughly studied by designers with the goal of reducing the area and power consumption of the hardware implementation of this cryptosystem. Until now, many architectures, for efficient VLSI realization of AES algorithm, have been proposed and their performance have been evaluated by using ASIC libraries and FPGA [2][3][4][5][6]. In this paper we are focusing on the implementation of the AES 128-bit, the SubBytes and the MixColumns transformations.…”

Section: Introductionmentioning

confidence: 99%

Performances of the AES design in 0.18μm CMOS technology

Mestiri

Machhout

Tourki

2012

7th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era

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The Advanced Encryption Standard (AES) has been studied by designers with the goal to improve its performances in terms of area, power consumption and frequency. In this paper, we present the implementation details of the AES encryption 128-bit, the MixColumns transformation and the SubBytes transformation. The latter can be implemented using a multi-stage PPRM architecture and composite field arithmetic in GF(((2 2 ) 2 ) 2 ). In addition, the MixColumns transformation is used in two architectures. The AES algorithm is implemented using 1.8V 0.18ȝm Complementary Metal Oxide Semiconductor (CMOS) technology. A low power consumption of 24.92 μW at 10 MHz and 23.2 mW at 67 MHz were achieved for the multi-stage PPRM architecture of SubBytes transformation and the AES encryption respectively. Compared to previous works, our AES implementations achieve good performance in term of power consumption.

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“…Unfortunately, it suffers from an unbreakable delay of memories that leads to a reduction in throughput [8,9]. S-box can be implemented using normal basis in composite field arithmetic, where it is possible to use pipelining and sub-pipelining techniques in order to decrease the critical path delay and increase the throughput [10,11].…”

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confidence: 99%

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

Oukili

Bri

2017

TELKOMNIKA

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The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.

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High speed S-box architecture for Advanced Encryption Standard

Cited by 6 publications

References 16 publications

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

Performances of the AES design in 0.18μm CMOS technology

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

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High speed S-box architecture for Advanced Encryption Standard

Cited by 6 publications

References 16 publications

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

Performances of the AES design in 0.18&#x03BC;m CMOS technology

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

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Performances of the AES design in 0.18μm CMOS technology