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Breast cancer is the most common cancer in women. It has the highest incidence rate and the highest mortality rate. In recent years, the incidence of breast cancer has become more and more important, it is becoming the first tumor killer for women around the world. Early diagnosis is the most important parameter for detecting cancerous tissue to prevent serious consequences. In this electronic paper, we present a new design of an ultra-wide-band circular microstrip patch antenna operating in the recommended FCC band GHz]) for the detection of breast tumors. The antenna is printed on an FR4 epoxy substrate with a dielectric permittivity r = 4.4 and loss tangent tan δ = 0.02. The results obtained are largely satisfying and prove that the proposed antenna is a candidate for biomedical applications.

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The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.