High speed vedic multiplier designs-A review

Bansal, Yogita; Madhu, Charu; Kaur, Pardeep

doi:10.1109/raecs.2014.6799502

Cited by 53 publications

(11 citation statements)

References 17 publications

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“…Vedic mathematics employs 16 sutras (algorithms) [4]. Only Urdhva Tiryakbyham sutra has been discussed here as in this paper it is implemented in the designing of faster and low power multiplier circuits.…”

Section: Vedic Mathematicsmentioning

confidence: 99%

Design of vedic multiplier using adiabatic logic

Singh

Sasamal

2015

2015 International Conference on Futuristic Trends on Computational Analysis and Knowledge Management (ABLAZE)

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A multiplier is a vital element in many arithmetic and logical units, digital signal processing and communication system. Therefore speed, area and power consumptions are the critical parameters for the designing of multiplier circuits. This paper presents a comparative study of binary Vedic multiplier using CMOS, PFAL and ECRL. The design is based on ancient Indian Vedic mathematics and the low power charge recovery logic. In Vedic multiplication, generation of partial sums and products is performed in single step so this along with adiabatic approach helps in realizing the high speed and low power operation of the binary Vedic multiplier design. The designs are simulated on Cadence Virtuoso Tool using UMC 180 nm CMOS technology. Simulation results show PFAL is the best technology as compared to CMOS, ECRL design for low power implementation of Vedic multiplier.

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Section: Vedic Mathematicsmentioning

confidence: 99%

Design of vedic multiplier using adiabatic logic

Singh

Sasamal

2015

2015 International Conference on Futuristic Trends on Computational Analysis and Knowledge Management (ABLAZE)

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“…Their implementation have lower area requirements and higher power dissipation, and in comparison with other memristive-CMOS threshold logic gates the proposed cell indicate lower area requirements and lower power dissipation [1]. Yogita Bansal, Charu Madhu, Pardeep Kaur work on High Speed Vedic Multiplier Designs on Urdhva Tiryakbhyam sutras.In their work the cmos layout of multiplier and adder cell is design [2].Aravind E Vijayan, Arlene John, Deepak Sen work on 8-bit Vedic Multipliers for Image Processing Application. Their design implemented on Xilinx Virtex 4 based FPGA board and the performance was evaluated using Xilinx ISim simulator [4].…”

Section: Literature Reviewmentioning

confidence: 99%

Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics

Fatima¹,

Tanveer²,

Shrman³

2015

IJCA

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Multiplication is the most time consuming process in various signal processing operations like Convolution, Circular Convolution, auto-correlation, and Cross Correlation, Image processing applications such as edge detection, microprocessors arithmetic and logical units etc. The multiplier circuit uses adder logic which reduces speed of operation due to its path propagation delay. The designs used offer tradeoffs between Computational time area, latency and throughput for performing multiplication. In this paper an ancient Indian Vedic mathematics sutras base multiplier have been proposed with Urdhva Tiryakbhyam sutra. In this methodology the length of input sequence used for multiplication varies from two to eight.

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“…The construction of a multiplier has been a challenging research problem for the last three-decades. Various approaches like Vedic multipliers and well-known algorithmic multipliers using shift and add, Wallace and Dadda tree multiplication, sequential multipliers, and array multipliers are adopted in the construction of a DSP [4]. The processor was injected with the problem of a large data set and a heavy payload in the current scenario [5].…”

Section: Introductionmentioning

confidence: 99%

Optimized Image Multiplication with Approximate Counter Based Compressor

Savio¹,

Deepa²,

Bharathiraja³

et al. 2022

Computers, Materials &Amp; Continua

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The processor is greatly hampered by the large dataset of picture or multimedia data. The logic of approximation hardware is moving in the direction of multimedia processing with a given amount of acceptable mistake. This study proposes various higher-order approximate counter-based compressor (CBC) using input shuffled 6:3 CBC. In the Wallace multiplier using a CBC is a significant factor in partial product reduction. So the design of 10-4, 11-4, 12-4, 13-4 and 14-4 CBC are proposed in this paper using an input shuffled 6:3 compressor to attain two stage multiplications. The input shuffling aims to reduce the output combination of the 6:3 compressor from 64 to 27. Design of 15-4, 10-4, 9-4, and 7-3 CBCs are performed using the proposed 6:3 compressor and the results obtained are compared with the existing models. These existing models are constructed using multiplexers and 5-3 CBC. When compared to input shuffled 5-3 the proposed 6:3 compressor shows better results in terms of area, power and delay. An approximation is performed on the 6:3 compressor to further reduce the computational energy of the system which is optimal for multimedia applications. The major contribution of this work is the development of two stage multiplier using various proposed CBC. All designs of the approximate compressor (AC) and true compressor (TC) are analysed with 8 x 8 and 16 x 16 image multiplication. The proposed multipliers also provide adequate levels of accuracy, according to the MATLAB simulations, in addition to greater hardware efficiency. As the result approximate circuits over image processing shows the stunning performance in many deep learning network in the current research which is only oriented to multimedia.

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High speed vedic multiplier designs-A review

Cited by 53 publications

References 17 publications

Design of vedic multiplier using adiabatic logic

Design of vedic multiplier using adiabatic logic

Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics

Optimized Image Multiplication with Approximate Counter Based Compressor

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