High-speed VLSI architectures for soft-output viterbi decoding

Joeressen, O.J.; Vaupel, M.; Meyr, H.

doi:10.1007/bf02109383

Cited by 24 publications

(9 citation statements)

References 13 publications

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“…The SMU shown in Fig. 5 (a) has a similar structure to the SMU in [4]. However, our SMU is based on TBA and does not have registers to store the decoded bits while the SMU in [4] is based on REA.…”

Section: A Tmumentioning

confidence: 98%

“…Many researchers have studied the SOVA decoder to improve its performance in terms of BER, power, and area at algorithm and architecture levels. Twostep SOVA [4], which separates decoding process into two processes called survivor and update processes, allows us to implement the turbo decoder with less complexity when compared with the original SOVA. In [5], a high throughput SOVA decoder with the register exchange algorithm (REA) has been implemented.…”

Section: Introductionmentioning

confidence: 99%

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Power and area efficient turbo decoder implementation for mobile wireless systems

Han

Erdogan

Arslan

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

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The authors present a low power and area efficient turbo soft-input soft-output (SISO) decoder based on two-step soft-output Viterbi algorithm (SOVA) targeting wireless mobile communication systems. Our turbo SISO decoder is based on trace back algorithm (TBA) and saves area and power by replacing the FIFO memory with an additional transition metric unit (TMU). The paper presents the implementation of SOVA decoder for constraint lengths K=3, 4, and 5, describing the design methodology and evaluation environment. Simulation results are provided showing up to 20% power saving and 46% area saving compared to a conventional SOVA decoder implementation.

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Section: A Tmumentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Power and area efficient turbo decoder implementation for mobile wireless systems

Han

Erdogan

Arslan

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

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“…The generator function g 0 equals 13 8 , and g 1 equals 15 8 in octal representation. The throughput requirements needed for terminal applications are 384kbps for the Turbodecoder.…”

Section: Gpp Parametersmentioning

confidence: 99%

“…This results in coding rates of 1/2 and 1/3. The generator functions for the rate 1/2 code are G 0 equals 753 8 and G 1 equals 561 8 , and for the rate 1/3 code they are G 0 equals 557 8 , G 1 equals 663 8 , and G 2 equals 711 8 . The maximum block length is 504, the tail sequence, which forces the encoder back into the all-zero state after all data bits are encoded, adds another 8 bits to the block.…”

Section: Gpp Parametersmentioning

confidence: 99%

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Channel decoder architecture for 3G mobile wireless terminals

Berns¹,

Kreiselmaier²,

Wehn³

Proceedings Design, Automation and Test in Europe Conference and Exhibition

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Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In thirdgeneration (3G) wireless systems channel coding techniques must serve both voice and data users whose requirements considerably vary. Thus the Third Generation Partnership Project (3GPP) standard offers two coding techniques, convolutional-coding for voice and Turbo-coding for data services. In this paper we present a combined channel decoding architecture for 3G terminal applications. It outperforms a solution based on two separate decoders due to an efficient reuse of computational hardware and memory resources for both decoders. Moreover it supports blind transport format detection. Special emphasis is put on low energy consumption.

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