High Speed VLSI Design CCMP AES Cipher for WLAN (IEEE 802.11i)

Abstract

The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper, we propose a high speed, non-pipelined FPGA implementation of the AES-CCMP (Counter-mode/CBC-MAC Protocol) cipher for wireless LAN using Xilinx development tools and Virtex-It Pro FPGA circuits. IEEE 802.11i defines the AES-based cipher system, which is operated on CCMP Mode. All the modules in this core are described by using Verilog 2001 language. The developed AES CCMP core is aimed at providing high speed with sufficient security. The encryption/decryption data path operates at 194/148MHz resulting in a throughput of 2.257 Gbits/sec for the encryption and 1.722 Gbits/sec for decryption. Compared to software implementation, migrating to hardware provides higher level of security and faster encryption speed. A comparison is provided between our design and similar existing implementations.

Study on E-Paper Controller Integrated with DRM

“…In scheme II, TCPU-D(II) =TD-CPU(II)=0. As in [6], there is significant difference between the hardware AES decryption and the software decryption. That means, TD(III)=TD(IV)<<TD(II).…”

“…These contain 3.960Mb data. As in [6], AES algorithm based on hardware can reach a performance of 1.722 Gb/s for decryption. It means hardware can process 34.44Mb data in one frame; these are larger than an image of 1920*1080 pixels, 16 depth bits.…”

CCMP Advanced Encryption Standard Cipher For Wireless Local Area Network (IEEE 802.11i): A Comparison with DES and RSA

“…The implementation of AES-CCMP protocol and it is analyzed with the DES and RSA algorithm. The comparative analysis took part in the Wireless medium (Daemen and Rijmen, 1998;Doomun and Soyjaudah, 2008;Islam et al, 2008;NIST, 1993;Samiah et al, 2007;Sanchez-Avila and Sanchez-Reillo, 2001;Schneier and Whiting, 2000;Sivakumar and Velmurugan, 2007;Smyth et al, 2006;Stallings, 2013 Fig. 1.…”